
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
á
41
B. If the XRT73L00 is operating in the Hardware
Mode
Set both the LLB input pin (pin 14) and the RLB input
pin (pin 15) to “High”.
N
OTES
:
1. The Digital Local Loop-Back Mode feature works
even if the transmitter is turned off via the TXOFF
feature.
2. The XRT73L00 automatically declares an LOS
Condition any time it has been configured to oper-
ate in either the Analog Local Loop-Back or Digital
Local Loop-Back Modes. Consequently, the MUT-
ing -upon -LOS must be disabled prior to configur-
ing the device to operate in either of these local
Loop-Back modes.
T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
When the XRT73L00 is configured to operate in the
Remote Loop-Back Mode, it ignores any signals that
are input to the TPDATA and TNDATA input pins. The
XRT73L00 receives the incoming line signal via the
RTIP and RRING input pins. This data is processed
through the Receive Section of the XRT73L00 and
outputs to the Receive Terminal Equipment via the
RPOS, RNEG, RCLK1 and RCLK2 output pins. Addi-
tionally, this data is internally looped back into the
Pulse-Shaping block in the Transmit Section. At this
point, this data is routed through the remainder of the
Transmit Section of the XRT73L00 and transmitted
out onto the line via the TTIP and TRING output pins.
Figure 30 illustrates the path that the data takes in the
XRT73L00 when the chip is configured to operate in
the Remote Loop-Back Mode.
4.3
During Remote Loop-Back operation, any data which
is inputted via the RTIP and RRING input pins is also
outputted to the Terminal Equipment via the RPOS,
RNEG and RCLK output pins.
The XRT73L00 can be configured to operate in the
Remote Loop-Back Mode by employing either one of
the following two steps
If the XRT73L00 is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the RLB bit-field and a “0” in the LLB bit-field
in Command Register CR4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
1
1
F
IGURE
30. T
HE
R
EMOTE
L
OOP
-B
ACK
P
ATH
IN
THE
XRT73L00
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2/LCV
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path