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參數(shù)資料
| 型號(hào)： | XRT71D04IV |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 6/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATTENUATOR 4CH 80TQFP |
| 標(biāo)準(zhǔn)包裝： | 94 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3.135 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 托盤 |
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XRT71D04
á
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
13
The XRT71D04 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
The Jitter-Attenuator PLL
Timing Control Block
The 2-Channel 16/32 Bit FIFO
Serial Microprocessor Interface
1.0
JITTER ATTENUATOR PLL
1.1
BACKGROUND INFORMATION
1.1.1
Definition of Jitter
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digita signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.1.2
SONET STS-1 to DS3 Mapping
SONET equipment jitter criteria are specified as:
i) Jitter Transfer
ii) Jitter Tolerance
iii) Jitter Generation
1.2
JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
FIGURE 6. A TYPICAL CHANNEL_N OF THE XRT71D04 CONFIGURED TO OPERATE IN THE HOST MODE
HOST
Reset
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
RCLK_n
RPOS_n
RNEG_n
ICT
CS
SDI
SDO SClk
MClkn
Smoothed
Clock
Jittery
Clock
RRCLKES
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT71D04IVTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 4CH E3/DS3/STS1 JIT ATTEN DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT7250 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7250ES-PCI | 功能描述:界面開(kāi)發(fā)工具 Evaluation Board for XRT7250 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XRT7250IQ100 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7288 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
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