參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 131/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
3.3 V
V
CCIOPORH
1.2 V
V
CCPORH
V
CCIOPORL
V
(1.2 V)
V
/ V
(3.3 V)
CC
CCIO
CCP
nPORRST
8
6
7
9
3
V
CCPORL
V
IL(PORRST)
V
/ V
CCIO
CCP
V
CC
V
CCPORL
V
IL(PORRST)
V
IL
V
IL
V
IL
V
CCIOPORH
V
CCPORH
V
CCIOPORL
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.3.2
Power-Down Sequence
The different supplies to the device can be powered down in any order.
4.3.3
Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
4.3.3.1
nPORRST Electrical and Timing Requirements
Table 4-4. Electrical Requirements for nPORRST
NO Parameter
MIN
MAX
Unit
VCCPORL
VCC low supply level when nPORRST must be active during power-
0.5
V
up
VCCPORH
VCC high supply level when nPORRST must remain active during
1.14
V
power-up and become active during power down
VCCIOPORL
VCCIO / VCCP low supply level when nPORRST must be active during
1.1
V
power-up
VCCIOPORH
VCCIO / VCCP high supply level when nPORRST must remain active
3.0
V
during power-up and become active during power down
VIL(PORRST)
Low-level input voltage of nPORRST VCCIO > 2.5V
0.2 * VCCIO
V
Low-level input voltage of nPORRST VCCIO < 2.5V
0.5
V
3
tsu(PORRST)
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL
0
ms
during power-up
6
th(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
ms
7
tsu(PORRST)
Setup time, nPORRST active before VCC < VCCPORH during power
2
s
down
8
th(PORRST)
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
1
ms
9
th(PORRST)
Hold time, nPORRST active after VCC < VCCPORL
0
ms
tf(nPORRST)
500
2000
ns
Filter time nPORRST pin;
pulses less than MIN will be filtered out, pulses greater than MAX
will generate a reset.
Figure 4-1. nPORRST Timing Diagram
58
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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