Rev. 2.00 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Control DIGtest ADCtest NoCDS LowPwr OE DAC1pd DAC0pd AFEpd ADCpd PwrDwn Default 0 1 0 D9 D" />
參數(shù)資料
型號： XRD98L61ZEVAL
廠商： Exar Corporation
文件頁數(shù)： 4/38頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XRD98L61AIV
標準包裝： 1
系列： *
XRD98L61
12
Rev. 2.00
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Control
DIGtest ADCtest NoCDS
LowPwr
OE
DAC1pd DAC0pd
AFEpd
ADCpd
PwrDwn
Default
0
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FDAC FDAC[9] FDAC[8] FDAC[7] FDAC[6]
FDAC[5] FDAC[4] FDAC[3] FDAC[2] FDAC[1] FDAC[0]
Default
0
FDAC Register (Reg. 7, Address 000111)
The FDAC register is used to set the Fine Offset DAC in the Manual Calibration mode. See Calibration
Option, in the Black Level Offset Calibration section for more information.
Control Register (Reg. 8, Address 001000)
The Control register is used to set various test and power-down modes.
DIGtest=0, normal operation.
DIGtest=1, Exar test mode - do not use.
ADCtest=0, connects PGA output to ADC input.
ADCtest=1, connects ADCinP & ADCinN pins to ADC input.
NoCDS=0, connects CDS output to PGA input.
NoCDS=1, connects Test1 & Test2 pins to PGA inputs (CDS by-pass mode).
Low Power=0, normal operation.
Low Power=1, Exar test mode - do not use.
OE=0, digital outputs in high-Z state.
OE=1, digital outputs enabled.
DAC1pd=1, Utility DAC1 is powered down.
DAC0pd=1, Utility DAC0 is powered down.
AFEpd=0, normal operation.
AFEpd=1, CDS & PGA are powered down, do not use.
ADCpd=0, normal operation.
ADCpd=1, ADC is powered down, do not use.
PwrDwn=0, normal operation.
PwrDwn=1, the whole chip is powered down.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CDAC
CDAC[8] CDAC[7] CDAC[6] CDAC[5] CDAC[4] CDAC[3] CDAC[2] CDAC[1] CDAC[0]
Default
0
CDAC Register (Reg. 6, Address 000110)
The CDAC register is used to set the Coarse Offset DAC in the Manual Calibration mode.
See Calibration Option, in the Black Level Offset Calibration section for more information.
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