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參數(shù)資料
| 型號： | XRD98L61ZEVAL |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 3/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XRD98L61AIV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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11
Rev. 2.00
XRD98L61
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OB Lines
OBL[7]
OBL[6]
OBL[5]
OBL[4]
OBL[3]
OBL[2]
OBL[1]
OBL[0]
Default
0
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Calibration
Avg[2]
Avg[1]
Avg[0]
Mode
LFrame
DNS[1]
DNS[0]
FastCal
Hold
ManCal
Default
1
0
1
0
1
0
The Calibration register is used to set various options for the Black Level Offset Calibration.
Avg[2:0] set the number of OB pixels to average:
000 = 4 pixels (not recommended)
100 = 64 pixels
001 = 8 pixels (not recommended)
101 = 128 pixels (default)
010 = 16 pixels (not recommended)
110 = 256 pixels
011 = 32 pixels
111 = 512 pixels
Mode=0, selects Line mode calibration (use OB pixels at start or end of each line).
Mode=1, do not use.
LFrame=0, selects Line mode calibration.
LFrame=1, do not use.
DNS[1:0] selects the Digital Noise Suppression filter setting:
00 = off,
10 = medium,
01 = narrow,
11 = wide.
FastCal=0, disables speedup convergence option of the calibration feedback loop.
FastCal=1, enables an option to speedup convergence of the calibration feedback loop.
Hold=0, normal operation of calibration feedback loop.
Hold=1, stops all updates to the Coarse and Fine offset DAC accumulators.
ManCal=0, normal operation of calibration feedback loop.
ManCal=1, enables manual calibration. The offset DACs are set to the values in the CDAC and FDAC registers.
See the Black Level Offset Calibration section for more information.
WaitA Register (Reg. 3, Address 000011)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WaitB
WL[1]
WL[0]
Default
0
1
WaitB Register (Reg. 4, Address 000100)
The WaitA and WaitB registers are concatenated to make up the Wait register.
See OB Pixel calibration section for more information.
OB Lines Register (Reg. 5, Address 000101)
The OB Lines register is used by the Offset Calibration Logic to set the number of Optical Black lines used
for Calibration in the Frame Mode. Do not use.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WaitA
WL[11]
WL[10]
WL[9]
WL[8]
WL[7]
WL[6]
WL[5]
WL[4]
WL[3]
WL[2]
Default
0
Calibration Register (Reg. 2, Address 000010)
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