REV. 1.0.0 The 128 byte TX FIFO can be loaded with data or 128 byte " />
參數(shù)資料
型號: XR20M1280L40-0B-EB
廠商: Exar Corporation
文件頁數(shù): 2/63頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR20M1280L40
產(chǎn)品培訓(xùn)模塊: XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
已用 IC / 零件: XR20M1280L40
已供物品:
其它名稱: 1016-1627
XR20M1280
10
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
The 128 byte TX FIFO can be loaded with data or 128 byte RX FIFO data can be unloaded in one SPI write or
read sequence.
FIGURE 8. SPI FIFO WRITE
R/W ‘0’
A2 A1 A0
‘0’
X
D7D6 D5D4D3D2D1 D0D7D6D5D4 D3D2D1D0
SCL
SI
last bit
FIGURE 9. SPI FIFO READ
SCL
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
last bit
R/W ‘0’
A2
A1
A0
‘0’
X
SI
SO
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
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