REV. 1.0.0 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.13 Auto CTS Flow Control Automatic CTS fl" />
參數(shù)資料
型號(hào)： XR20M1280L40-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 14/63頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20M1280L40
產(chǎn)品培訓(xùn)模塊： XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
已用 IC / 零件： XR20M1280L40
已供物品： 板
其它名稱(chēng)： 1016-1627
XR20M1280
21
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.13
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 18):
Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an
interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend
transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after
the CTS# input is re-asserted (LOW), indicating more data may be sent.
FIGURE 18. AUTO RTS AND CTS FLOW CONTROL OPERATION
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
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