REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART 39 Interrupt Generation: LSR is by any of the LSR bits 1, 2, 3 and 4. RXRDY " />
參數(shù)資料
型號： XR17D154CV-F
廠商： Exar Corporation
文件頁數(shù)： 33/69頁
文件大?。?/td> 0K
描述： IC UART PCI BUS QUAD 144LQFP
產(chǎn)品培訓模塊： UART Product Overview
標準包裝： 60
特點： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
其它名稱： 1016-1289
xr
XR17D154
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
39
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by the a 4-char plus 12 bits delay timer if the RX FIFO level is less than the RX trigger
level.
TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control).
MSR is by any of the MSR bits, 0, 1, 2 and 3.
Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
CTS#/DSR# is by a change of state on the input pin (from LOW to HIGH) with auto flow control enabled,
EFR bit-7, and depending on selection of MCR bit-2.
RTS#/DTR# is when its receiver changes the state of the output pin (from LOW to HIGH) during auto RTS/
DTR flow control enabled by EFR bit-6 and selection of MCR bit-2.
Wake-up Indicator: when the UART comes out of sleep mode.
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
TXRDY interrupt is cleared by a read to the ISR register.
MSR interrupt is cleared by a read to the MSR register.
Xon or Xoff character interrupt is cleared by a read to ISR register.
Special character interrupt is cleared by a read to ISR register or after the next character is received.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
Wake-up Indicator is cleared by a read to the INT0 register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source Table 14).
TABLE 14: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
3
0
1
0
RXRDY (Receive Data Time-out)
4
0
1
0
TXRDY (Transmitter Holding Register Empty)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xon/Xoff or Special character)
7
1
0
CTS#/DSR#, RTS#/DTR# change of state
X
0
1
None (default)
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