REV. 1.4.3 5V PCI BUS OCTAL UART 19 1.2.6 SLEEP [31:24] - (default 0x00) The 8-bit Sleep register enables each UART separately to e" />
參數(shù)資料
型號(hào)： XR17C158IV
廠商： Exar Corporation
文件頁(yè)數(shù)： 11/67頁(yè)
文件大?。?/td> 0K
描述： IC UART PCI BUS OCTAL 144LQFP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 60
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 4.5 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
xr
XR17C158
REV. 1.4.3
5V PCI BUS OCTAL UART
19
1.2.6 SLEEP [31:24] - (default 0x00)
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power
consumption when the system needs to put the UART(s) to idle. All of these conditions must be satisfied for
the 158 to enter sleep mode:
no interrupts pending (INT0 = 0x00)
divisor is a non-zero value for all channels (ie. DLL = 0x1)
sleep mode is enabled for all 8 channels (SLEEP = 0xFF)
modem inputs for all channels are not toggling (MSR bits 0-3 = 0)
RX input pins for all channels are idling HIGH
The 158 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no
clock output as an indication that the device has entered the sleep mode.
The 158 resumes normal operation by any of the following:
a receive data start bit transition (HIGH to LOW) on the RX input of any channel
a data byte is loaded to the transmitter, THR or FIFO, of any channel
a change of logic state on any of the modem or general purpose serial inputs of any channel: CTS#, DSR#,
CD#, RI#
If the 158 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 158 is awakened by the modem inputs, a read
to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an in-
terrupt is pending from any channel. The 158 will stay in the sleep mode of operation until it is disabled by set-
ting Sleep = 0x00. The UART is ready after 32 crystal clocks to ensure full functionality. Also, a special interrupt
is generated with an indication of no pending interrupt. Reading INT0 will clear this special interrupt. Logic 0
(default) disables the sleep mode and logic 1 enables the sleep mode for each channel. The crystal oscillator
shuts down only when all 8 channels are in sleep mode.
1.2.7
Device Identification and Revision
There are two internal registers that provide device identification and revision, DVID and DREV registers. The
8-bit content in the DVID register provides device identification. A return value of 0x28 from this register
indicates the device is a XR17C158. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02
equals to revision B and so forth. This information is very useful to the software driver for identifying which
device it is communicating with and to keep up with revision changes.
DVID [15:8]
Device identification for the type of UART. The upper nibble indicates it is an XR17Cxxx series with lower
nibble indicating the number of channels.
Examples:
XR17C158 or XR17D158 = 0x28
XR17C154 or XR17D154 = 0x24
XR17C152 or XR17D152 = 0x22
DREV [7:0]
Revision number of the XR17C158. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
SLEEP Register
Individual UART Channel Sleep Enable
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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