
XR17C158
PCI BUS OCTAL UART
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REV. 1.1.3
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FUNCTIONAL DESCRIPTION
The XR17C158 (158) integrates the functions of 8 en-
hanced 16550 UARTs with the PCI Local Bus inter-
face and a non-volatile memory interface for PCI
bus’s plug-and-play auto-configuration, a 16-bit timer/
counter, 8 multi-purpose inputs/outputs, and an on-
chip oscillator. The PCI local bus is a synchronous
timing bus where all bus transactions are associated
to the bus clock of up to 33MHz. The 158 supports
32-bit wide read and write data transfer operations in-
cluding data burst mode through the PCI Local Bus
interface. Read and write data operations may be in
byte, word or double-word (DWORD) format. A single
32-bit interrupt status register provides interrupts sta-
tus for all 8 UARTs, timer/counter, multipurpose in-
puts/outputs, and a special sleep wake up indicator.
There are three sets of register in the device. First,
the PCI local bus configuration registers for PCI auto
configuration. A set of device configuration registers
for overall control, 32-bit wide transmit and receive
data transfer, and monitoring of the 8 UART channels.
Lastly, each UART channel has its own 16550 UART
compatible configuration register set for individual
channel control, status, and byte wide data transfer.
Each UART has 64-byte FIFOs, automatic RTS/CTS
or DTR/DSR hardware flow control with hysteresis
control, automatic Xon/Xoff and special character
software flow control, programmable transmit and re-
ceive FIFO trigger level, FIFO level counters, infrared
encoder and decoder (IrDA ver. 1.0), programmable
baud rate generator with a prescaler of 1X or 4X, and
data rate up to 6.25 Mbps at 8X sampling clock. The
XR17C158 bus timing and drive capability meets the
PCI local bus specification revision 2.2 for 5 volt oper-
ation over the temperature range. Although it does
not meet the 3.3V speed specification, it is capable of
operating up to 22MHz with 5 volt tolerant inputs. The
XR17C158 is available in a thin 144-pin TQFP
(20x20x1.0mm) package in commercial and industrial
temperature ranges.
PCI L
OCAL
B
US
I
NTERFACE
This is the host interface and it meets the PCI Local
Bus Specification revision 2.2. The PCI local bus op-
erations are synchronous meaning each transaction
is associated to the bus clock. The XR17C158 can
operate with the bus clock of up to a 33MHz. Data
transfers operation can be formatted in 8-bit, 16-bit,
24-bit or 32-bit wide. With 32-bit data operations, it
pushes the data transfer rate on the bus up to 132
MByte/sec. This increases the overall system’s com-
munication performance up to 16 times better than
the 8-bit ISA bus. See PCI local bus specification revi-
sion 2.2 for bus operation details.
PCI Local Bus Configuration Space
Registers
A set of PCI local bus configuration space
register is
provided. These registers provide the PCI local bus
operating system with the card’s vendor ID, device ID,
sub-vendor ID, product model number, and resources
and capabilities. The PCI local bus operating system
collects this data from all the cards on the bus during
the auto configuration phase that follows immediately
after a power up or system reset/reboot. After it has
sorted out all devices on the bus, it defines and down-
load the operating conditions to the cards. One of the
definitions is the base address loaded into the Base
Address Register (BAR) where the card will be oper-
ating in the PCI local bus memory space.
EEPROM Interface
An external 93C46 EEPROM is only used to store the
vendor’s ID and model number, and the sub-vendor’s
ID and product model number. This information is
only used with the plug-and-play auto configuration of
the PCI local bus. These data provide automatic
hardware installation onto the PCI bus. The EEPROM
interface consists of 4 signals, EEDI, EEDO, EECS,
and EECK. The EEPROM is not needed when auto
configuration is not required in the application. How-
ever, If your design requires non-volatile memory for
other purpose. It is possible to store and retrieve data
on the EEPROM through a special PCI device config-
uration register. See application note DAN112 for its
programming details.
1.0
The XR17C158 UART has three different sets of reg-
isters as shown in Figure 3. The PCI local bus config-
uration space registers are for plug-and-play auto-
configuration when connecting the device to a the
PCI bus. This auto-configuration feature makes instal-
lation very easy into a PCI system and it is part of the
PCI local bus specification. The second register set is
the device configuration registers that are accessible
directly from the PCI bus for programming general op-
erating conditions of the device and monitoring the
status of various functions. These registers are
mapped into 4K of the PCI bus memory address
space. These functions include all 8 channel UART’s
interrupt control and status, 16-bit general purpose
timer control and status, multipurpose inputs/outputs
control and status, sleep mode, soft-reset, and device
identification and revision. And lastly, each UART
channel has its own set of internal UART configura-
tion registers for its own operation control and status
reporting. All 8 sets of channel registers are embed-
ded inside the device configuration registers space,
which provides faster access. The following para-
graphs describe all 3 sets of registers in detail.
XR17C158 REGISTERS