參數(shù)資料
型號(hào)： XR17C158IV
英文描述： UART
中文描述： 異步
文件頁(yè)數(shù)： 14/55頁(yè)
文件大小： 734K
代理商： XR17C158IV
á
PCI BUS OCTAL UART
XR17C158
REV. 1.1.3
14
1.2.2
[TIMERMSB, TIMELSB, TIMER, TIMECNTL]
(
DEFAULT
0
X
XX-XX-00-00)
A 16-bit down-count timer for general purpose timer
or counter. Its clock source may be selected from in-
ternal crystal oscillator or externally on pin TMRCK.
The timer can be set to be a single-shot for a one-
time event or re-triggerable for continue interval. An
General Purpose 16-bit Timer/Counter.
interrupt may be generated in the INT Register when
the timer times out. It is controlled through 4 configu-
ration registers [TIMERCNTL, TIMER, TIMELSB,
TIMERMSB]. These registers provide start/stop and
re-triggerable or one-shot operation. The time-out
output of the Timer can be set to generate an inter-
rupt for system or event alarm.
T
ABLE
5: UART C
HANNEL
[7:0] I
NTERRUPT
S
OURCE
E
NCODING
P
RIORITY
B
IT
[
N
+2]
B
IT
[
N
+1]
B
IT
[
N
]
I
NTERRUPT
S
OURCE
(
S
)
x
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only within channel 0, reserved in other channels.
TIMER Time-out. Available only within channel 0, reserved in other chan-
nels.
T
ABLE
6: UART C
HANNEL
[7:0] I
NTERRUPT
C
LEARING
:
RXRDY and RXRDY Time-out is clear by reading data in the RX FIFO until it falls below the trigger level.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel reg-
ister set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
F
IGURE
5. T
IMER
/C
OUNTER
CIRCUIT
.
TMRCK
OSC. CLOCK
TIMERCNTL [3]
16-Bit
Timer/Counter
TIMERCNTL [2]
Re-trigger
Single-shot
TIMERCNTL [1]
Start/Stop
TIMERCNTL [0]
Timer Interrupt, Ch-0 INT=7
Time-out
Timer Interrupt Enable
Single/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
0
1
0
1
No Interrupt
Clock
Select
TIMERCNTL [4]
0
1
MPIO[0]
MPIOLVL[0]
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