- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1975 > XR17C158IV-F (Exar Corporation)IC UART PCI BUS OCTAL 144LQFP PDF資料下載
參數(shù)資料
| 型號： | XR17C158IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 37/67頁 |
| 文件大小： | 0K |
| 描述： | IC UART PCI BUS OCTAL 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 8 |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1646 XR17C158IV-F-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
XR17C158
xr
5V PCI BUS OCTAL UART
REV. 1.4.3
42
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. Reading the
XCHAR register will indicate which character (Xoff or Xon) was received last. If it is a special character
interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from LOW to HIGH.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.8.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode (legacy term that refers to "block transfer mode"). The DMA and FIFO modes are
defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software. DMA is a legacy term used for block transfer mode. DMA does not stand for "Direct Memory Ac-
cess."
Logic 0 = Set DMA to mode 0 (default).
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
The FCTR bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load. Table 14 below shows the selections. EFR bit-4 must be set to ‘1’ before these
bits can be accessed. Note that the receiver and the transmitter cannot use different trigger tables. Whichever
selection is made last applies to both the RX and TX side.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR17D152CM-F | IC UART PCI BUS DUAL 100TQFP |
| XR17D154CV-F | IC UART PCI BUS QUAD 144LQFP |
| XR17D158IV-F | IC UART PCI BUS OCTAL 144LQFP |
| XR17V252IM | IC UART PCI BUS DUAL 100TQFP |
| XR17V254IV-F | IC UART PCI BUS QUAD 144LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17C158IVTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C158IVTR-F |
| XR17D152 | 制造商:EXAR 制造商全稱:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART |
| XR17D152CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART |
| XR17D152CM-0A-EVB | 功能描述:界面開發(fā)工具 Supports D152 100 ld TQFP, PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR17D152CM-F | 功能描述:UART 接口集成電路 3.3V-5V 64B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。