REV. 1.3.2 32 4.6 Internal Loopback Each UART channel provides an internal loopback capability f" />
參數(shù)資料
型號: XR17C154CV
廠商: Exar Corporation
文件頁數(shù): 26/62頁
文件大小: 0K
描述: IC UART PCI BUS QUAD 144LQFP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 60
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-LQFP(20x20)
包裝: 托盤
XR17C154
xr
5V PCI BUS QUAD UART
REV. 1.3.2
32
4.6
Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 16 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held HIGH (idle or de-asserted state), and the CTS#, DSR#
CD# and RI# inputs are ignored.
4.7
UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING
The 4 sets of UART configuration registers are decoded using address lines A8 to A11 as show below. Ad-
dress lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with
EXAR enhanced feature registers located on the upper 8 addresses.
FIGURE 16. INTERNAL LOOP BACK
A11
A10
A9
A8
UART CHANNEL
SELECTION
0
1
0
1
0
1
0
2
0
1
0
3
TX [3:0]
RX [3:0]
Mod
em
/
General
Pu
rp
os
e
Control
Logic
In
tern
al
Bu
s
L
in
es
an
d
Co
n
tro
lSig
n
als
RTS# [3:0]
MCR bit-4=1
VCC
Transmit Shift
Register
Receive Shift
Register
CTS# [3:0]
DTR# [3:0]
DSR# [3:0]
RI# [3:0]
CD# [3:0]
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
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XR17C154CVTR-F 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C154CVTR-F
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