REV. 1.3.2 20 MPIOLVL [7:0] (default 0x00) Output pin level control and input level status. The status of the " />
參數(shù)資料
型號: XR17C154CV
廠商: Exar Corporation
文件頁數(shù): 13/62頁
文件大?。?/td> 0K
描述: IC UART PCI BUS QUAD 144LQFP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝: 60
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
XR17C154
xr
5V PCI BUS QUAD UART
REV. 1.3.2
20
MPIOLVL [7:0] (default 0x00)
Output pin level control and input level status. The status of the input pin(s) is read on this register and output
pins are controlled on this register. A logic 0 (default) sets the output to low and a logic 1 sets the output pin to
high. The MPIO interrupt will clear upon reading this register.
MPIO3T [7:0] (default 0x00)
Output pin tri-state control. A logic 0 (default) sets the output to active level per register MPIO3T settling, a
logic 1 sets the output pin to tri-state.
MPIOINV [7:0] (default 0x00)
Input inversion control. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic
level.
MPIOSEL [7:0] (default 0xFF)
Multipurpose input/output pin select. This register defines the functions of the pins. A logic 1 (default) defines
the pin for input and a logic 0 for output.
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOLVL Register
Multipurpose Output Level Control
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO3T Register
Multipurpose Output 3-state Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINV Register
Multipurpose Input Signal Inversion Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOSEL Register
Multipurpose Input/Output Selection
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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