General Purpose 16-bit Timer/Counter [TIMERM" />
參數(shù)資料
型號： XR16V598IQ100-F
廠商： Exar Corporation
文件頁數(shù)： 19/58頁
文件大?。?/td> 0K
描述： IC UART FIFO 16B OCTAL 100QFP
標(biāo)準(zhǔn)包裝： 66
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 16 字節(jié)
規(guī)程： RS485
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤
XR16V598
26
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.3
3.1.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
The 598 includes a 16-bit general purpose timer/counter. Its clock source may be selected from internal crystal
oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or re-
triggerable for a periodic signal. An interrupt may be generated when the timer times out and will show up as a
Channel 0 interrupt (see Table 9). It is controlled through 4 configuration registers [TIMERCNTL, TIMER,
TIMELSB, TIMERMSB]. These registers provide start/stop and re-triggerable or one-shot operation (see
below). The time-out output of the Timer can be set to generate an interrupt for system or event
alarm.
3.1.2.1
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit-0 of the
TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Default value is zero (timer disabled) upon powerup and reset.
3.1.2.2
TIMER [7:0] Reserved
3.1.2.3
TIMERCNTL [7:0] Register
The bits 3:0 of this register are used to issue commands. The commands are self-clearing, so reading this
register does not show the last written command. Reading this register returns a value of 0x01 when there is a
Timer interrupt pending and 0x00 at all other times.
TABLE 9: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY
Bit
2
Bit
1
Bit
0
INTERRUPT SOURCE(S) AND CLEARING
x
0
None or wake-up indicator
1
0
1
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
2
0
1
0
RXRDY Time-out: Cleared same way as RXRDY INT.
3
0
1
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
4
1
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clears after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR
register.
5
1
0
1
Reserved.
6
1
0
Reserved.
7
1
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
Reserved in other channels.
TIMERMSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10
Bit-9 Bit-8
TIMERLSB Register
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1 Bit-0
16-Bit Timer/Counter Programmable Registers
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