REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 3.2 UART Channel Configuration Registers The " />
參數(shù)資料
型號(hào)： XR16M698IQ100-F
廠(chǎng)商： Exar Corporation
文件頁(yè)數(shù)： 25/58頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 32B OCTAL 100QFP
標(biāo)準(zhǔn)包裝： 66
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 32 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤(pán)
XR16M698
31
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
3.2
UART Channel Configuration Registers
The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8
addresses. The 8 sets of UART configuration registers are decoded using address lines A0 to A3 as shown
below.
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS
ADDRESS
REGISTER
READ/WRITE
COMMENTS
A3 A2 A1 A0
16550 COMPATIBLE
0 0 0 0
RHR - Receive Holding Reg
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 0 0
DLL - Divisor LSB
Read/Write
LCR[7] = 1
0 0 0 1
DLM - Divisor MSB
Read/Write
LCR[7] = 1
0 0 1 0
DLD - Divisor Fractional Part
Read/Write
LCR[7] = 1
0 0 0 1
IER - Interrupt Enable Reg
Read/Write
LCR[7] = 0
0 0 1 0
ISR - Interrupt Status Reg
FCR - FIFO Control Reg
Read-only
Write-only
LCR[7] = 0
0 0 1 1
LCR - Line Control Reg
Read/Write
0 1 0 0
MCR - Modem Control Reg
Read/Write
0 1 0 1
LSR - Line Status Reg
Read-only
0 1 1 0
MSR - Modem Status Reg
- Auto RS-485 Delay
Read-only
Write-only
0 1 1 1
SPR - Scratch Pad Reg
Read/Write
ENHANCED REGISTER
1 0 0 0
FCTR
Read/Write
1 0 0 1
EFR - Enhanced Function Reg
Read/Write
1 0 1 0
Reserved
Read-only
1 0 1 1
Reserved
Read-only
1 1 0 0
Xoff-1 - Xoff Character 1
Xchar
Write-only
Read-only
Xon,Xoff Rcvd.
Flags
1 1 0 1
Xoff-2 - Xoff Character 2
Reserved
Write-only
Read-only
1 1 1 0
Xon-1 - Xon Character 1
Reserved
Write-only
Read-only
1 1 1 1
Xon-2 - Xon Character 2
Reserved
Write-only
Read-only
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