參數(shù)資料
型號(hào)： XR16C854IJ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 52/53頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 128B QUAD 68PLCC
標(biāo)準(zhǔn)包裝： 19
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC
包裝： 管件
其它名稱： XR16C854IJ-F-ND
XR16C854/854D
8
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 3.1.0
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
Factory Test Mode
If the IOR#, IOW# and CS# pins are all asserted (at a logic 0) simultaneously, the 854 will enter a Factory Test
Mode. The 854 is not operational in this mode and will exit this mode only upon a power cycle.
XTAL2
26
36
41
O
Crystal or buffered clock output.
16/68#
-
31
36
Intel or Motorola Bus Select (input with internal pull-up).
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will
operate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.
Motorola bus interface is not available on the 64 pin package.
CLKSEL
21
30
35
I
Baud-Rate-Generator Input Clock Prescaler Select for channels A-
D. This input is only sampled during power up or a reset. Connect
to VCC for divide by 1 and GND for divide by 4. MCR[7] can over-
ride the state of this pin following a reset or initialization. See MCR
bit-7 and
Figure 6 in the Baud Rate Generator section.
CHCCLK
-
42
I
This input provides the clock for UART channel C. An external
16X baud clock or the crystal oscillator’s output, XTAL2, must be
connected to this pin for normal operation. This input may also be
used with MIDI (Musical Instrument Digital Interface) applications
when an external MIDI clock is provided.
RESET
(RESET#)
27
37
43
I
When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes the Reset pin (active high). In this case, a 40 ns mini-
mum logic 1 pulse on this pin will reset the internal registers and all
outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset
period (Table 19). When 16/68# pin is at a logic 0 for Motorola bus
interface, this input becomes Reset# pin (active low). This pin
functions similarly, but instead of a logic 1 pulse, a 40 ns minimum
logic 0 pulse will reset the internal registers and outputs.
Motorola bus interface is not available on the 64 pin package.
VCC
4, 35, 52
13, 47,
64
10, 61,
86
Pwr
2.97V to 5.5V power supply. All input pins, except XTAL1, are 5V
tolerant.
GND
14, 28,
45, 61
6, 23, 40,
57
20, 46,
71, 96
Pwr
Power supply common, ground.
N.C.
-
1, 2, 3, 4,
26, 27,
28, 29,
30, 51,
52, 53,
54, 55,
77, 78,
79, 80
No Connection. These pins are not used in either the Intel or
Motorola bus modes.
Pin Description
NAME
64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
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XR16C854IV 制造商:Exar Corporation 功能描述:
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