參數(shù)資料
型號(hào): XR16C854IJ-F
廠商: Exar Corporation
文件頁(yè)數(shù): 49/53頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 128B QUAD 68PLCC
標(biāo)準(zhǔn)包裝: 19
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: XR16C854IJ-F-ND
53
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2013 EXAR Corporation
Datasheet April 2013.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XR16C854/854D
REV. 3.1.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REVISION HISTORY
DATE
REVISION
DESCRIPTION
November 1999
Rev 1.0
Removed Preliminary designation.
February 2002
Rev 2.0
Changed to standard style format. Text descriptions were clarified and sim-
plified (eg. DMA operation, FIFO mode vs. Non-FIFO mode operations etc).
Corrected RTS Hysteresis character values in Table 15. Clarified timing dia-
grams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing
symbols. Added TCS, TRWS and TRST.
May 2003
Rev 2.1
Added patent number and updated Block Diagram.
June 2003
Rev 2.2
Added and updated device status in Ordering Information.
January 2004
Rev 3.0
Changed to standard style format. Clarified sleep mode conditions. Devices
with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs
(except for XTAL1). Devices with top mark date code of "DC YYWW" and
older do not have 5V tolerant inputs.
August 2005
Rev 3.0.1
Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP"
to "LQFP" to be consistent with the JEDEC and Industry norms.
April 2013
Rev 3.1.0
Updated AC Electrical Characteristics. Updated Ordering Information:
Removed discontinued part numbers, added Green/RoHS part numbers and
TR part numbers. Updated package drawings.
ECN: 1318-05 04/30/2013
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