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參數(shù)資料
| 型號： | XR16C854DCV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 50/53頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B QUAD 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 特點： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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XR16C854/854D
6
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 3.1.0
INTB
INTC
INTD
(N.C.)
12
37
43
21
49
55
18
63
69
O
When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
become the interrupt outputs for channels B, C, and D. The output
state is defined by the user through the software setting of MCR[3].
The interrupt outputs are set to the active mode when MCR[3] is
set to a logic 1 and are set to the three state mode when MCR[3] is
set to a logic 0 (default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
Motorola bus interface is not available on the 64 pin package.
INTSEL
-
65
87
I
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-
D pins or override MCR bit-3 and enable the interrupt outputs.
Interrupt outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and
disable the interrupt output pins. In this mode, MCR bit-3 is set to
a logic 1 to enable the continuous output. See MCR bit-3 descrip-
tion for full detail. This pin must be at logic 0 in the Motorola bus
interface mode. Due to pin limitations on 64 pin packages, this pin
is not available. To cover this limitation, two 64 pin LQFP pack-
ages versions are offered. The XR16C854D operates in the con-
tinuous interrupt enable mode by bonding this pin to VCC
internally.
TXRDYA#
TXRDYB#
TXRDYC#
TXRDYD#
-
5
25
56
81
O
UART channels A-D Transmitter Ready (active low). The outputs
provide the TX FIFO/THR status for transmit channels A-D. See
Table 5. If these outputs are unused, leave them unconnected.
RXRDYA#
RXRDYB#
RXRDYC#
RXRDYD#
-
100
31
50
82
O
UART channels A-D Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channels A-D. See
Table 5. If these outputs are unused, leave them unconnected.
TXRDY#
-
39
45
O
Transmitter Ready (active low). This output is a logically wire-
ORed status of TXRDY# A-D. See Table 5. If this output is
unused, leave it unconnected.
RXRDY#
-
38
44
O
Receiver Ready (active low). This output is a logically wire-ORed
status of RXRDY# A-D. See Table 5. If this output is unused,
leave it unconnected.
FSRS#
-
76
I
FIFO Status Register Select (active low input with internal pull-up).
The content of the FSTAT register is placed on the data bus when
this pin becomes active. However it should be noted, D0-D3 con-
tain the inverted logic states of TXRDY# A-D pins, and D4-D7 the
logic states (un-inverted) of RXRDY# A-D pins. Address line is not
required when reading this status register.
Pin Description
NAME
64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
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| XR16C854IJTR-F | IC UART FIFO 128B QUAD 68PLCC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C854DCVTR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 128Byte FIFO 3.3V/5V 64-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR16C854DCVTR-F |
| XR16C854DIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO |
| XR16C854DIV-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854DIV-F | 制造商:Exar Corporation 功能描述:IC QUAD UART 2MBPS 5.5V 64-LQFP |
| XR16C854DIVTR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 128Byte FIFO 3.3V/5V 64-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR16C854DIVTR-F |
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