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XR16C854/854D
40
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 3.1.0
TABLE 19: UART RESET CONDITIONS FOR CHANNELS A-D
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
EMSR
Bits 7-0 = 0x00
FLVL
Bits 7-0 = 0x00
TRG
Bits 7-0 = 0x00
FC
Bits 7-0 = 0x00
FCTR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
FSTAT
Bits 7-0 = 0xFF
I/O SIGNALS
RESET STATE
TX
Logic 1
IRTX
Logic 0
RTS#
Logic 1
DTR#
Logic 1
RXRDY#
Logic 1
TXRDY#
Logic 0
INT
XR16C854 = Three-State Condition
XR16C854D = Logic 0
IRQ#
Logic 1 (68 mode, INTSEL = 0)