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參數資料
| 型號： | XR16C850IQ |
| 英文描述： | UART|CMOS|QFP|52PIN|PLASTIC |
| 中文描述： | 異步|的CMOS | QFP封裝| 52PIN |塑料 |
| 文件頁數： | 15/49頁 |
| 文件大?。?/td> | 690K |
| 代理商： | XR16C850IQ |
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XR16C854/XR16C854D
3.3V AND 5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0
15
1) when the FIFO becomes empty. The transmit
empty interrupt is enabled by IER bit-1. The TSR flag
(LSR bit-6) is set when TSR/FIFO becomes empty.
2.11 R
ECEIVER
The receiver section contains an 8-bit Receive Shift
Register (RSR) and 128 bytes of FIFO which includes
a byte-wide Receive Holding Register (RHR). The
RSR uses the 16X clock for timing. It verifies and vali-
dates every bit on the incoming character in the mid-
dle of each data bit. On the falling edge of a start or
false start bit, an internal receiver counter starts
counting at the 16X clock rate. After 8 clocks the start
bit period should be at the center of the start bit. At
this time the start bit is sampled and if it is still a logic
0 it is validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false charac-
ter. The rest of the data bits and stop bits are sam-
pled and validated in this same manner to prevent
false framing. If there were any error(s), they are re-
ported in the LSR register bits 2-4. Upon unloading
the receive data byte from RHR, the receive FIFO
pointer is bumped and the error tags are immediately
updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready in-
terrupt upon receiving a character or delay until it
reaches the FIFO trigger level. Furthermore, data de-
livery to the host is guaranteed by a receive data
ready time-out interrupt when data is not received for
4 word lengths as defined by LCR[1,0] plus 12 bits
time. This is equivalent to 3.7-4.6 character times.
The RHR interrupt is enabled by IER bit-0.
2.11.1 Receive Holding Register (RHR) - Read-
Only
The Receive Holding Register is an 8-bit register that
holds a receive data byte from the Receive Shift Reg-
ister. It provides the receive data interface to the host
processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are
for the 3 error tags to be reported in LSR register.
When the FIFO is enabled by FCR bit-0, the RHR
contains the first data character received by the FIFO.
After the RHR is read, the next character byte is load-
ed into the RHR and the errors associated with the
current data byte are immediately updated in the LSR
bits 2-4.
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
Transmit Data Shift Register
(TSR)
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
RX FIFO
THR
16X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
TXFIFO1
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相關代理商/技術參數 |
參數描述 |
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| XR16C854 | 制造商:EXAR 制造商全稱:EXAR 功能描述:并轉串4串口擴展芯片 |
| XR16C854CJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C854CJ-0A-EVB | 功能描述:UART 接口集成電路 Supports C854 68 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854CJTR-F | 制造商:Exar Corporation 功能描述:XR16C854CJTR-F |
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