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參數(shù)資料
| 型號： | XR16C850IP |
| 英文描述： | UART|CMOS|DIP|40PIN|PLASTIC |
| 中文描述： | 異步|的CMOS |雙酯| 40PIN |塑料 |
| 文件頁數(shù)： | 31/49頁 |
| 文件大?。?/td> | 690K |
| 代理商： | XR16C850IP |
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XR16C854/XR16C854D
3.3V AND 5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0
31
This is a 8-bit general purpose register for the user to
store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (de-
fault) after a reset or a power off-on cycle.
4.11 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR)
This register replaces SPR (during a Write) and is ac-
cessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-
Only)
When Scratchpad Swap (FCTR[6]) is asserted, EM-
SR bits 1-0 controls what mode the FIFO Level
Counter is operating in.
During Alternate RX/TX FIFO Counter Mode, the first
value read after EMSR bits 1-0 have been asserted
will always be the RX FIFO Counter. The second val-
ue read will correspond with the TX FIFO Counter.
The next value will be the RX FIFO Counter again,
then the TX FIFO Counter and so on and so forth.
EMSR[3:2]: Reserved
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
4.12 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
The FIFO Level Register replaces the Scratchpad
Register (during a Read) when FCTR[6] = 1. Note
that this is not identical to the FIFO Data Count Reg-
ister which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the
RX FIFO or the TX FIFO or both depending on EM-
SR[1:0]. See Table 14 for details.
4.13 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value which is used to calcu-
late the baud rate:
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.14 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
This register contains the device ID (0x14 for
XR16C854). Prior to reading this register, DLL and
DLM should be set to 0x00.
4.15 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
T
ABLE
14: S
CRATCHPAD
S
WAP
S
ELECTION
FCTR[6] EMSR[1]
0
1
1
1
1
EMSR[0] Scratchpad is
X
Scratchpad
0
RX FIFO Counter Mode
1
TX FIFO Counter Mode
0
RX FIFO Counter Mode
1
Alternate RX/TX FIFO
Counter Mode
X
0
0
1
1
T
ABLE
15: A
UTO
RTS H
YSTERESIS
EMSR
B
IT
-5
EMSR
B
IT
-4
FCTR
B
IT
-1
FCTR
B
IT
-0
RTS#
H
YSTERESIS
(C
HARACTERS
)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
±4
±6
±8
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
±8
±16
±24
±32
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
±40
±44
±48
±52
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
±12
±20
±28
±36
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C850IQ | UART|CMOS|QFP|52PIN|PLASTIC |
| XR17C158CV | UART |
| XR17C158IV | UART |
| XR215CP | IC-PHASE LOCKED LOOP |
| XR215 | Monolithic Phase Locked Loop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C850IQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART|CMOS|QFP|52PIN|PLASTIC |
| XR16C854 | 制造商:EXAR 制造商全稱:EXAR 功能描述:并轉(zhuǎn)串4串口擴展芯片 |
| XR16C854CJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C854CJ-0A-EVB | 功能描述:UART 接口集成電路 Supports C854 68 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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