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參數(shù)資料
| 型號(hào)： | XR16C850IP |
| 英文描述： | UART|CMOS|DIP|40PIN|PLASTIC |
| 中文描述： | 異步|的CMOS |雙酯| 40PIN |塑料 |
| 文件頁(yè)數(shù)： | 16/49頁(yè) |
| 文件大?。?/td> | 690K |
| 代理商： | XR16C850IP |
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XR16C854/XR16C854D
3.3V AND 5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0
á
16
N
OTE
:
Table-B selected as Trigger Table for Figure 10
(Table 11 ).
2.12 A
UTO
RTS H
ARDWARE
F
LOW
C
ONTROL
Automatic RTS hardware flow control is used to pre-
vent data overrun to the local receiver FIFO. The
RTS# output is used to request remote unit to sus-
pend/resume data transmission. The auto RTS flow
control features is enabled to fit specific application
requirement (see Figure 11):
- Enable auto RTS flow control using EFR bit-6.
- The auto RTS function must be started by asserting
RTS# output pin (MCR bit-1 to logic 1 after it is en-
abled).
- Enable RTS interrupt through IER bit-6 (after setting
EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-
5 will be set to logic 1.
2.13 A
UTO
RTS H
YSTERESIS
The 854 has a new feature that provides flow control
trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
(
E
L
64 bytes by 11-bit
wide FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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| XR16C850IQ | UART|CMOS|QFP|52PIN|PLASTIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C850IQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART|CMOS|QFP|52PIN|PLASTIC |
| XR16C854 | 制造商:EXAR 制造商全稱:EXAR 功能描述:并轉(zhuǎn)串4串口擴(kuò)展芯片 |
| XR16C854CJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C854CJ-0A-EVB | 功能描述:UART 接口集成電路 Supports C854 68 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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