REV. 2.1.1 46 FIGURE 24" />
參數(shù)資料
型號: XR16C2852IJTR-F
廠商: Exar Corporation
文件頁數(shù): 41/51頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 44PLCC
標準包裝: 500
特點: *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
XR16C2852
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.1
46
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
Data in
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TX
TXRDY#
IOW#
INT*
D0:D7
S
TXDMA
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
T
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
T
SI
ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
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