REV. 2.1.1 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 33 MSR[7]: CD Input Status Normally this bit is the complement of the CD# i" />
參數(shù)資料
型號(hào): XR16C2852IJTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 27/51頁(yè)
文件大小: 0K
描述: IC UART FIFO 128B 44PLCC
標(biāo)準(zhǔn)包裝: 500
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
xr
XR16C2852
REV. 2.1.1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
33
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.11
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12
Enhanced Mode Select Register (EMSR)
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will
always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next
value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.
EMSR[3:2]: Reserved
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0]
SCRATCHPAD IS
0
X
Scratchpad
1
0
RX FIFO Counter Mode
1
0
1
TX FIFO Counter Mode
1
0
RX FIFO Counter Mode
1
Alternate RX/TX FIFO
Counter Mode
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