- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1974 > XR16C2852IJ-F (Exar Corporation)IC UART FIFO 128B 44PLCC PDF資料下載
參數(shù)資料
| 型號： | XR16C2852IJ-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 50/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 128B 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱： | 1016-1659 XR16C2852IJ-F-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁
XR16C2852
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.1
8
2.5
Channel A and B Internal Registers
Each UART channel in the 2852 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the 2852 offers enhanced feature registers (AFR,
EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware
flow control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable,
FIFO trigger level control, FIFO level counters, and simultaneous writes to both channels. All the register
functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 21.
2.6
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be considered, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.7
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2852 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-
3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. In this mode, the 2852 sets the TXRDY# pin when the
transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following
table shows their behavior. Also see Figures 20 through 25.
TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
FUNCTION
1
X
UART de-selected
0
1
Channel A selected
0
Channel B selected
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C850IMTR-F | IC UART FIFO 128B 48TQFP |
| XR16C854IQ-F | IC UART FIFO 128B QUAD 100QFP |
| XR16C864IQ-F | IC UART FIFO 128B QUAD 100QFP |
| XR16L2450IJ-F | IC UART FIFO 1B DUAL 44PLCC |
| XR16L2550IJ-F | IC UART FIFO 16B DUAL 44PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2852IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR-16C450CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C450CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C452CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C550CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。