REV. 2.1.1 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 5 NOTE: P" />
參數(shù)資料
型號： XR16C2852IJ-F
廠商： Exar Corporation
文件頁數(shù)： 45/51頁
文件大?。?/td> 0K
描述： IC UART FIFO 128B 44PLCC
標準包裝： 27
特點： *
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1659
XR16C2852IJ-F-ND
xr
XR16C2852
REV. 2.1.1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
5
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
RTSB#
23
O
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3]. If this output is not used, leave it unconnected.
CTSB#
28
I
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
DTRB#
27
O
UART channel B Data-Terminal-Ready (active low) or general purpose output. If this
output is not used, leave it unconnected.
DSRB#
29
I
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used.
CDB#
30
I
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used.
RIB#
31
I
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used.
MFB#
19
O
Multi-Function Output Channel B. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a
reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See
Table 2 on page 9 for more details.
If this output is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
11
I
Crystal or external clock input.
XTAL2
13
O
Crystal or buffered clock output.
RESET
21
I
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset period (see Table 16 on
VCC
44, 33
Pwr
2.97V to 5.5V power supply. All inputs are 5V tolerant for devices with top mark date
code of "F2 YYWW" and newer.
GND
22, 12
Pwr
Power supply common, ground.
Pin Description
NAME
44-PLCC
PIN #
TYPE
DESCRIPTION
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