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參數(shù)資料
| 型號： | XQR4062XL-3CB228M |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 201K |
| 代理商： | XQR4062XL-3CB228M |
QPRO XQR4000XL Radiation Hardened FPGAs
DS071 (v1.1) June 25, 2000
Product Specification
This Material Copyrighted by Its Respective Manufacturer
1-800-255-7778XQR4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Global Low Skew Clock, Input Setup and Hold Times
(1,2)
Symbol
Description
Device
(1)
-3
Units
Min
No Delay
T
PSN
/T
PHN
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQR4013XL
1.2 / 3.2
ns
XQR4036XL
1.2 / 5.5
ns
XQR4062XL
1.2 / 7.0
ns
Partial Delay
T
PSP
/T
PHP
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQR4013XL
6.1 / 0.0
ns
XQR4036XL
6.4 / 1.0
ns
XQR4062XL
6.7 / 1.2
ns
Full Delay
T
PSD
/T
PHD
Global early clock and IFF
(3)
XQR4013XL
6.4 / 0.0
ns
XQR4036XL
6.6 / 0.0
ns
XQR4062XL
6.8 / 0.0
ns
Notes:
1.
The XQR4013XL, XQR4036XL, and XQR4062XL have significantly faster partial and full delay setup times than
other devices.
Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the
furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing
analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
IFF = Input Flip-Flop or Latch
FCL = Fast Capture Latch
2.
3.
4.
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