參數(shù)資料
型號(hào)： XQR4062XL-3CB228M
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 201K
代理商： XQR4062XL-3CB228M
DS071 (v1.1) June 25, 2000
Product Specification
This Material Copyrighted by Its Respective Manufacturer
1-800-255-7778
1
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
XQR4000XL Series Features
Radiation-hardened FPGAs for space and satellite
applications
Guaranteed total ionizing dose
Latch-up immune
Low soft upset rate
Guaranteed to meet full electrical specifications over
–55°C to +125°C
Available in -3 speed
System featured FPGAs
-
SelectRAM memory: on-chip ultra-fast RAM with
·
synchronous write option
·
dual-port RAM option
-
Abundant flip-flops
-
Flexible function generators
-
Dedicated high-speed carry logic
-
Wide edge decoders on each edge
-
Hierarchy of interconnect lines
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal distribution
networks
System performance beyond 60 MHz
Flexible array architecture
Low power segmented routing architecture
Systems-oriented features
-
IEEE 1149.1-compatible boundary scan logic
support
-
Individually programmable output slew rate
-
Programmable input pull-up or pull-down resistors
-
12 mA sink current per output
Configured by loading binary file
-
Unlimited reprogrammability
Readback capability
-
Program verification
-
Internal node observability
Development system runs on most common computer
platforms
-
Interfaces to popular design environments
-
Fully automatic mapping, placement and routing
-
Interactive design editor for design optimization
Highest capacity: over 130,000 usable gates
Buffered interconnect for maximum speed
New latch capability in configurable logic blocks
Improved VersaRing
I/O interconnect for better fixed
pinout flexibility
-
Virtually unlimited number of clock signals
Optional multiplexer or 2-input function generator on
device outputs
5V tolerant I/Os
Advanced 0.35
μ
process
Processed on Xilinx QML line
0
QPRO XQR4000XL Radiation
Hardened FPGAs
DS071 (v1.1) June 25, 2000
0
2
Product Specification
R
Table 1:
XQR4000XL Series Radiation Hardened Field Programmable Gate Arrays
Max.
Logic
Gates
(No RAM)
(No Logic)
Device
Logic
Cells
Max. RAM
Bits
Typical
Gate Range
(Logic and
RAM)
(1)
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
User
I/O
Packages
XQR4013XL
1,368
13,000
18,432
10,000 - 30,000
24 x 24
576
1,536
192
CB228
XQR4036XL
3,078
36,000
41,472
22,000 - 65,000
36 x 36
1,296
3,168
288
CB228
XQR4062XL
5,472
62,000
73,728
40,000 - 130,000
48 x 48
2,304
5,376
384
CB228
Notes:
1.
Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
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