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參數(shù)資料
| 型號(hào)： | XPC850ZT80BU |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 15/76頁(yè) |
| 文件大?。?/td> | 825K |
| 代理商： | XPC850ZT80BU |
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MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
15
Layout Practices
B28b
CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS = 10
or ACS = 11, EBDF = 0
—
12.00
—
14.00
—
13.00
0.250
50.00
ns
B28c
CLKOUT falling edge to
WE[0–3] negated GPCM write
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1
7.00
14.00 11.00 18.00
9.00
16.00
0.375
50.00
ns
B28d
CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1
—
14.00
—
18.00
—
16.00
0.375
50.00
ns
B29
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, CSNT = 0
3.00
—
6.00
—
4.00
—
0.250
50.00
ns
B29a
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0
8.00
—
13.00
—
11.00
—
0.500
50.00
ns
B29b
CS negated to D[0–31],
DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0
3.00
—
6.00
—
4.00
—
0.250
50.00
ns
B29c CS negated to D[0–31], DP[0–3]
high-Z GPCM write access,
TRLX = 0, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 0
8.00
—
13.00
—
11.00
—
0.500
50.00
ns
B29d
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0
28.00
—
43.00
—
36.00
—
1.500
50.00
ns
B29e
CS negated to D[0–31], DP[0–3]
high-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 0
28.00
—
43.00
—
36.00
—
1.500
50.00
ns
B29f
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
5.00
—
9.00
—
7.00
—
0.375
50.00
ns
B29g
CS negated to D[0–31], DP[0–3]
high-Z GPCM write access
TRLX = 0, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1
5.00
—
9.00
—
7.00
—
0.375
50.00
ns
Table 6-6. Bus Operation Timing
1
(continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
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|---|---|
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