參數(shù)資料
型號(hào): XIO2200AZGW
廠商: Texas Instruments
文件頁(yè)數(shù): 99/202頁(yè)
文件大?。?/td> 0K
描述: IC PCI-EXPRESS/BUS BRIDGE 176BGA
產(chǎn)品培訓(xùn)模塊: PCI Express Basics
標(biāo)準(zhǔn)包裝: 126
應(yīng)用: PCI Express 至 PCI 轉(zhuǎn)換橋
接口: PCI
電源電壓: 1.35 V ~ 1.65 V,3 V ~ 3.6 V
封裝/外殼: 176-LFBGA
供應(yīng)商設(shè)備封裝: 176-BGA MICROSTAR(15x15)
包裝: 托盤(pán)
安裝類型: 表面貼裝
產(chǎn)品目錄頁(yè)面: 882 (CN2011-ZH PDF)
配用: XIO2200AEVM-ND - XIO2200AEVM
其它名稱: 296-19567
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1394 PHY Configuration Space
175
March 5 2007 June 2011
SCPS154C
10.4 Vendor-Dependent Register
The vendor-dependent page provides access to the special control features of the controller, as well as to
configuration and status information used in manufacturing test and debug. This page is selected by writing
7 to the Page_Select field in base register 7. Table 107 shows the configuration of the vendor-dependent
page, and Table 108 shows the corresponding field descriptions.
Table 107. Page 7 (Vendor-Dependent) Register Configuration
BIT POSITION
ADDRESS
0
1
2
3
4
5
6
7
1000
NPA
Reserved
Link_Speed
1001
Reserved for test
1010
Reserved for test
1011
Reserved for test
1100
Reserved for test
1101
Reserved for test
1110
Reserved for test
1111
Reserved for test
Table 108. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
NPA
1
RW
Null-packet actions flag. This bit instructs the PHY layer to not clear fair and priority requests when a null packet
is received with arbitration acceleration enabled. If this bit is set to 1b, then fair and priority requests are cleared
only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits),
and malformed packets (less than 8 data bits) do not clear fair and priority requests. If this bit is cleared to 0b,
then fair and priority requests are cleared when any non-ACK packet is received, including null packets or
malformed packets of less than 8 bits. This bit is cleared to 0b by system (hardware) reset and is unaffected by
bus reset.
Link_Speed
2
RW
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY and
LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during
self-ID; the PHY layer identifies itself as S400 capable to its peers regardless of the value in this field. This field is
set to 10b (S400) by system (hardware) reset and is unaffected by bus reset.
10.5 Power-Class Programming
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field
(bits 21–23) of the transmitted self-ID packet. Table 109 shows the descriptions of the various power classes.
The default power-class value is loaded following a system (hardware) reset, but is overridden by any value
subsequently loaded into the Pwr_Class field in register 4.
Table 109. Power Class Descriptions
PC0–PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self-powered and provides a minimum of 15 W to the bus.
010
Node is self-powered and provides a minimum of 30 W to the bus.
011
Node is self-powered and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the link.
101
Reserved
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
Not Recommended for New Designs
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