
Feature/Protocol Descriptions
36
March 5 2007 June 2011
SCPS154C
Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP
is received on the PCI Express interface and the link cannot be transitioned to L1.
3.12 1394a OHCI Controller Functionality
3.12.1
1394a OHCI Power Management
The 1394a OHCI controller complies with the PCI Bus Power Management Interface Specification. The
controller supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power
management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.
Table 313 identifies the supported power management registers within the 1394a OHCI configuration
register map.
Table 313. 1394a OHCI Configuration Register Map
REGISTER NAME
OFFSET
Power management capabilities
Next item pointer
Capability ID
44h
PM data
Power management control/status register bridge support extensions
Power management control/status (CSR)
48h
3.12.2
1394a OHCI and VAUX
The 1394a OHCI function within the XIO2200A is powered by VDD_MAIN only. Therefore, during the D3cold
power management state, VAUX is not supplied to the 1394a OHCI function.
This implies that the 1394a OHCI function does not implement sticky bits and needs to be initialized after a
D3cold power management state. An external serial EEPROM interface is available to initialize critical
configuration register bits. The EEPROM download is triggered by the deassertion of the PERST input.
Otherwise, the BIOS will need to initialize the 1394a OHCI function.
3.12.3
1394a OHCI and Reset Options
The 1394a OHCI function is completely reset by the internal power-on reset feature, by the GRST input, or
by the PCI Express reset (PERST) input. This includes all EEPROM loadable bits, power management
functions, and all remaining configuration register bits and logic.
A PCI Express training control hot reset or the PCI bus configuration register reset bit (SRST) excludes the
EEPROM loadable bits, power management functions, and 1394 PHY. All remaining configuration registers
and logic are reset.
If the OHCI controller is in the power management D2 or D3 state or if the OHCI configuration register reset
bit (SoftReset) is set, the OHCI controller DMA logic and link logic is reset.
Finally, if the OHCI configuration register PHY reset bit (ISBR) is set, the 1394 PHY logic is reset.
3.12.4
1394a OHCI PCI Bus Master
As a bus master, the 1394 OHCI function supports the memory commands specified in
Table 314. The
commands include memory read, memory read line, memory read multiple, memory write, and memory write
and invalidate.
The read command usage for read transactions of greater than two data phases are determined by the
selection in bits 9:8 (MR_ENHANCE field) of the PCI miscellaneous configuration register at offset F0h (see
Section
7.22). For read transactions of one or two data phases, a memory read command is used.
The write command usage is determined by the MWI_ENB bit 4 of the command configuration register at offset
04h (see Section
4.3). If bit 4 is asserted and a memory write starts on a cache boundary with a length greater
than one cache line, then memory write and invalidate commands are used. Otherwise, memory write
commands are used.
Not Recommended for New Designs