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| 型號(hào)： | XCR3384XLSERIES |
| 英文描述： | 384 Macrocell CPLD |
| 中文描述： | 384宏單元CPLD |
| 文件頁數(shù)： | 27/43頁 |
| 文件大?。?/td> | 396K |
| 代理商： | XCR3384XLSERIES |
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Table 12: XCR3320 Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
SAMPLE/PRELOAD
(00010)
Boundary-Scan Register
Description
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal
operation of the component to be taken and examined. It also allows data values to be
loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register prior to
selection of the other boundary-scan test instructions.
The mandatory EXTEST instruction allows testing of off-chip circuitry and board level
interconnections. Data would typically be loaded onto the latched parallel outputs of
Boundary-Scan Shift-Register using the SAMPLE/PRELOAD instruction prior to
selection of the EXTEST instruction.
Places the 1-bit bypass register between the tdi and tdo pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation. The BYPASS instruction can be entered by holding tdi at a
constant high value and completing an Instruction-Scan cycle.
Selects the IDCODE register and places it between tdi and tdo, allowing the IDCODE
to be serially shifted out of tdo. The IDCODE instruction permits blind interrogation of
the components assembled onto a printed circuit board. Thus, in circumstances where
the component population may vary, it is possible to determine what components exist
in a product.
The HIGHZ instruction places the component in a state in which all of its system logic
outputs are placed in an inactive drive state (e.g., high impedance). In this state, an
in-circuit test system may drive signals onto the connections normally driven by a
component output without incurring the risk of damage to the component. The HIGHZ
instruction also forces the Bypass Register between tDI and tDO.
The INTEST instruction allows testing of the on-chip system logic while the component
is assembled on the board. The boundary-scan register is connected between TDI and
TDO. Using the INTEST instruction, test stimuli are shifted in one at a time and applied
to the on-chip system logic. The test results are captured into the boundary-scan
register and are examined by subsequent shifting, Data would typically be loaded onto
the latched parallel outputs of boundary-scan shift-register stages using the
SAMPLE/PRELOAD instruction prior to selection of the INTEST instruction.
EXTEST
(00000)
Boundary-Scan Register
BYPASS
(11111)
Bypass Register
IDCODE
(00001)
Boundary-Scan Register
HIGHZ
(00101)
Bypass Register
INTEST
(00011)
Boundary-Scan Register
NOTE: Following use of the INTEST instruction, the on-chip system logic may be in an
indeterminate state that will persist until a system reset is applied. Therefore, the
on-chip system logic may need to be reset on return or normal (i.e., non-test)
operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3512XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:CoolRunner XPLA3 CPLD |
| XCR3512XL-10FG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
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| XCR3512XL-10FGG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FGG324I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
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