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| 型號(hào)： | XCR3320-7TQ144C |
| 文件頁數(shù)： | 26/43頁 |
| 文件大?。?/td> | 396K |
| 代理商： | XCR3320-7TQ144C |
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JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of spe-
cialized test equipment. BST provides the ability to test the
external connections of a device, test the internal logic of
the device, and capture data from the device during normal
operation. BST provides a number of benefits in each of the
following areas:
Testability
-
Allows testing of an unlimited number of
interconnects on the printed circuit board
-
Testability is designed in at the component level
-
Enables desired signal levels to be set at specific
pins (Preload)
-
Data from pin or core logic signals can be examined
during normal operation
Reliability
-
Eliminates physical contacts common to existing test
fixtures (e.g.,
“
bed-of-nails
”
)
-
Degradation of test equipment is no longer a
concern
-
Facilitates the handling of smaller, surface-mount
components
-
Allows for testing when components exist on both
sides of the printed circuit board
Cost
-
Reduces/eliminates the need for expensive test
equipment
Reduces test preparation time
Reduces spare board inventories
-
-
The Xilinx XCR3320's JTAG interface includes a TAP Port
and a TAP Controller, both of which are defined by the IEEE
1149.1 JTAG Specification. As implemented in the Xilinx
XCR3320, the TAP Port includes five pins (refer to
Table 10
) described in the JTAG specification: t
CK
, t
MS
, t
DI
,
t
DO
, and t
RSTN
. These pins should be connected to an
external pull-up resistor to keep the JTAG signals from
floating when they are not being used.
Table 11
defines the dedicated pins used by the mandatory
JTAG signals for the XCR3320.
The JTAG specifications define two sets of commands to
support boundary-scan testing: high-level commands and
low-level commands. High-level commands are executed
via board test software on an a user test station such as
automated test equipment, a PC, or an engineering work-
station (EWS). Each high-level command comprises a
sequence of low level commands. These low-level com-
mands are executed within the component under test, and
therefore must be implemented as part of the TAP Control-
ler design. The set of low-level boundary-scan commands
implemented in the XCR3320 is defined in
Table 11
. By
supporting this set of low-level commands, the XCR3320
allows execution of all high-level boundary-scan com-
mands.
Table 10: JTAG Pin Description
Pin
tck
Name
Description
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the tdi and tdo pins,
respectively. tck is also used to clock the TAP Controller state machine.
Serial input pin selects the JTAG instruction mode. tms should be driven high during
user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of tck.
Serial output pin for instructions and test data. Data is shifted out on the falling edge of
tck. The signal is tri-stated if data is not being shifted out of the device.
Forces TAP controller to test logic reset state. This signal is active low.
tms
Test Mode Select
tdi
tdo
Test Data Input
Test Data Output
trstn
Test Reset
Table 11: XCR3320 JTAG Pinout by Package Type
Device: XCR3320
(Pin Number / Macrocell #)
t
DL
U5
42
t
CK
V4
41
t
MS
W4
43
t
DO
Y4
44
t
RSTN
L18
97
256-pin PBGA
160-pin LQFP
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