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| 型號： | XCR3320-7TQ144C |
| 文件頁數(shù)： | 19/43頁 |
| 文件大?。?/td> | 396K |
| 代理商： | XCR3320-7TQ144C |
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.
Synchronous Peripheral Mode
In the synchronous peripheral mode, byte-wide data is
input into D[7:0] on the rising edge of the cclk input. The
first data byte is clocked in on the second cclk after hdc
goes high. Subsequent data bytes are clocked in on every
eighth rising edge of cclk. The process repeats until all of
the data is loaded into the XCR3320. The serial data
begins shifting out on dout 0.5 cycles after the parallel data
was loaded. It requires additional cclks after the last byte is
loaded to complete the shifting.
Figure 21
shows the inter-
face for synchronous peripheral mode. When configuring a
single device, the frequency of cclk can be up to 10 MHz.
As with master modes, this mode can be used for the lead
XCR3320 for daisy-chained devices. Note that the cclk fre-
quency for daisy-chained operation is limited to 1 MHz.
Also note that CS1 is a multi-function pin, which means that
it is available as a user I/O during normal device operation.
As with all user I/O on the XCR3320, CS1 has an internal
pull-down resistor that is automatically activated if the I/O
pin is not used (see
“
Terminations
”
on page 8
for more
information). If CS1 is left attached to V
CC
after configura-
tion, and it is not used as an I/O, the internal pull-down must
be disabled or a path from V
CC
to ground is created. To dis-
able the pull-down, use the XPLA property statement
‘
signal name:pin number
tri-state’
to disable
the resistor.
Table 6: Master Parallel Configuration Mode Timing Characteristics
Symbol
t
AV
t
S
t
H
t
CL
t
CH
t
D
f
C
Parameter
Min.
0
60
0
357
357
-
0.6
Nom.
-
Max.
200
-
-
833
833
300
1.4
Unit
ns
ns
ns
ns
ns
ns
MHz
cclk to address valid
D[7:0] setup time to cclk high
D[7:0] hold time from cclk high
cclk low time
cclk high time
cclk to dout delay
cclk frequency
M3 = 1
M3 = 1
500
500
M3 = 1
1.0
SP00675
MICRO
–
PROCESSOR
OR
SYSTEM
D[7:0]
done
crcerrn
cclk
prgmn
cs1
cs0n
M2
M1
M0
V
CC
8
XCR3320
dout
TO DAISY-CHAINED
DEVICES
M3
resetn
SPMI
EXTERNALLY CONTROLLED
IF DESIRED
SEE TABLE 9
V
CC
wrn
Figure 21: Synchronous Peripheral Configuration
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