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參數(shù)資料
| 型號(hào)： | XCR3128A-10VQ100I |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | PLD |
| 英文描述： | CPLD with Enhanced Clocking |
| 中文描述： | EE PLD, 10 ns, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大小： | 268K |
| 代理商： | XCR3128A-10VQ100I |
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
2
The XCR3128A CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128A also includes an industry-standard, IEEE
1149.1, JTAG interface through which In-System Program-
ming (ISP) and reprogramming of the device are sup-
ported.
XPLA Architecture
shows a high-level block diagram of a 128 macro-by a zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
Logic Block Architecture
Figure 2
illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells
’
flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Archi-
tecture section for details). The PAL array consists of a pro-
grammable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a pro-
grammable OR array. The PAL array provides a high speed
path through the array, while the PLA array provides
increased product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
PD
of the XCR3128A device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 1.5 ns.
So the total pin-to-pin t
PD
for the XCR3128A using six to 37
product terms is 9 ns (7.5 ns for the PAL + 1.5 ns for the
PLA).
Figure 1: Xilinx XPLA CPLD Architecture
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
ZIA
LOGIC
BLOCK
LOGIC
BLOCK
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
LOGIC
BLOCK
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
SP00464
LOGIC
BLOCK
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| XCR3128A-10TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-10TQ128I | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | CPLD with Enhanced Clocking |
| XCR3128A-12VQ100C | CPLD with Enhanced Clocking |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128A-12TQ128C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-15TQ128C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
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