參數(shù)資料
型號(hào)： XCR3128A-10VQ100I
廠商： XILINX INC
元件分類： PLD
英文描述： CPLD with Enhanced Clocking
中文描述： EE PLD, 10 ns, PQFP100
封裝： PLASTIC, VQFP-100
文件頁數(shù)： 12/17頁
文件大?。?/td> 268K
代理商： XCR3128A-10VQ100I
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
12
AC Electrical Characteristics
1
For Commercial Grade Devices
Commercial: 0
°
C
≤
T
AMB
≤
+70
°
C; 3.0V
≤
V
CC
≤
3.6V
Symbol
Parameter
7
10
12
Unit
Min.
2
Max.
7.5
Min.
2
Max.
10
Min.
2
Max.
12
t
PD_PAL
Propagation delay time, input (or
feedback node) to output through PAL
Propagation delay time, input (or
feedback node) to output through PAL +
PLA
Clock to out (global synchronous clock
from pin)
Setup time (from input or feedback node)
through PAL
Setup time (from input or feedback node)
through PAL + PLA
Hold time
2
Clock High time
2
Clock Low time
2
Input rise time
2
Input fall time
2
Maximum FF toggle rate
2
1/(t
CH
+ t
CL
)
Maximum internal frequency
2
1/(t
SUPAL
+ t
CF
)
Maximum external frequency
2
1/(t
SUPAL
+ t
CO
)
Output buffer delay time
2
Input (or feedback node) to internal
feedback node delay time through PAL
2
Input (or feedback node) to internal
feedback node delay time through
PAL+PLA
2
Clock to internal feedback node delay
time
2
Delay from valid V
CC
to valid reset
2
Input to output disable
2, 3
Input to output valid
2
Input to register preset
2
Input to register reset
2
ns
t
PD_PLA
3
9
3
11.5
3
13.5
ns
t
CO
2
5.5
2
7
2
8
ns
t
SU_PAL
3.5
4
6
ns
t
SU_PLA
5
5.5
7.5
ns
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
0
0
0
ns
ns
ns
ns
ns
MHz
MHz
2
2
2.5
2.5
3
3
100
100
100
100
100
100
250
143
200
118
167
91
f
MAX3
111
91
71
MHz
t
BUF
t
PDF_PAL
2
2
2
8
ns
ns
2
5.5
2
7.5
2
t
PDF_PLA
3
7
3
9
3
9.5
ns
t
CF
3.5
4.5
5
ns
t
INIT
t
ER
t
EA
t
RP
t
RR
Notes:
20
8
8
9
9
20
9.5
9.5
9.5
9.5
20
10
10
10
10
μ
s
ns
ns
ns
ns
Figure 6
3. Output C
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