參數(shù)資料
型號： XCR3128A-10TQ128I
廠商： XILINX INC
元件分類： PLD
英文描述： CPLD with Enhanced Clocking
中文描述： EE PLD, 10 ns, PQFP128
封裝： PLASTIC, TQFP-128
文件頁數(shù)： 14/17頁
文件大小： 268K
代理商： XCR3128A-10TQ128I
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
14
AC Electrical Characteristics
1
For Industrial Grade Devices
Industrial: -40
°
C
≤
T
AMB
≤
+85
°
C; 2.7V
≤
V
CC
≤
3.6V
Symbol
Parameter
10
15
Unit
Min.
Max.
Min.
Max.
t
PD_PAL
Propagation delay time, input (or feedback node) to out-
put through PAL
2
10
2
15
ns
t
PD_PLA
Propagation delay time, input (or feedback node) to out-
put through PAL + PLA
3
11.5
3
16.5
ns
t
CO
t
SU_PAL
t
SU_PLA
Clock to out (global synchronous clock from pin)
2
7
2
8
ns
Setup time (from input or feedback node) through PAL
4
6
ns
Setup time (from input or feedback node) through
PAL + PLA
5.5
7.5
ns
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
BUF
t
PDF_PAL
Hold time
0
0
ns
Clock High time
3
4
ns
Clock Low time
3
4
ns
Input rise time
100
100
ns
Input fall time
Maximum FF toggle rate
2
1/(t
CH
+ t
CL
)
Maximum internal frequency
2
1/(t
SUPAL
+ t
CF
)
Maximum external frequency
2
1/(t
SUPAL
+ t
CO
)
Output buffer delay time
2
100
100
ns
167
125
MHz
111
87
MHz
91
77
MHz
2
2
ns
Input (or feedback node) to internal feedback node delay
time through PAL
2
2
8
2
9
ns
t
PDF_PLA
Input (or feedback node) to internal feedback node delay
time through PAL+PLA
2
Clock to internal feedback node delay time
2
Delay from valid V
CC
to valid reset
2
Input to output disable
2, 3
Input to output valid
2
Input to register preset
2
Input to register reset
2
3
9.5
3
10.5
ns
t
CF
t
INIT
t
ER
t
EA
t
RP
t
RR
5
5.5
ns
20
20
μ
s
10
12
ns
10
12
ns
10
12
ns
10
12
ns
Notes:
Figure 6
3. Output C
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