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參數(shù)資料
| 型號(hào)： | XCR3064A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 64 Macrocell CPLD With Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的64宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 64宏單元CPLD在增強(qiáng)時(shí)鐘（帶增強(qiáng)時(shí)鐘控制的64個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大小： | 171K |
| 代理商： | XCR3064A |
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
DS037 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
2
This product has been discontinued. Please see
for details.The XCR3064A CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BPMicrosystems, SMS, and others. The XCR3064A
also includes an industry-standard, IEEE 1149.1, JTAG
interface through which In-System Programming (ISP) and
reprogramming of the device are supported.
XPLA Architecture
Figure 1
shows a high level block diagram of a 64 macro-
cell device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
Logic Block Architecture
Figure 2
illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells' flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Archi-
tecture Section for details). The PAL array consists of a pro-
grammable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a pro-
grammable OR array. The PAL array provides a high speed
path through the array, while the PLA array provides
increased product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin T
PD
of the XCR3064A device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 1.5 ns.
So the total pin-to-pin T
PD
for the XCR3064A using six to
37 product terms is 9.0 ns (7.5 ns for the PAL + 1.5 ns for
the PLA).
Figure 1: Xilinx XPLA CPLD Architecture
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC1
MC2
MC16
I/O
MC1
MC2
MC16
SP00439
ZIA
LOGIC
BLOCK
LOGIC
BLOCK
I/O
36
16
16
MC1
MC2
MC16
36
16
16
I/O
MC1
MC2
MC16
LOGIC
BLOCK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3064XL-6CP56C | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ100I | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ44C | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ44I | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-6VQ44C | XCR3064XL 64 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3064A-10CP56C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
| XCR3064A-10PC44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
| XCR3064A-10PC44I | 制造商:Xilinx 功能描述: |
| XCR3064A-10VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
| XCR3064A-10VQ44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
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