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參數(shù)資料
| 型號： | XCR3064A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 64 Macrocell CPLD With Enhanced Clocking(帶增強(qiáng)時鐘控制的64宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 64宏單元CPLD在增強(qiáng)時鐘（帶增強(qiáng)時鐘控制的64個宏單元復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 171K |
| 代理商： | XCR3064A |
R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
13
www.xilinx.com
1-800-255-7778
DS037 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.AC Electrical Characteristics
1
For Industrial Grade Devices
Industrial: -40
°
C
≤
T
AMB
≤
+85
°
C; 2.7V
≤
V
CC
≤
3.6V
Symbol
Parameter
10
12
Unit
Min.
2
3
Max.
10
11.5
Min.
2
3
Max.
12
13.5
T
PD_PAL
T
PD_PLA
Propagation delay time, input (or feedback node) to output through PAL
Propagation delay time, input (or feedback node) to output through
PAL + PLA
Clock to out (global synchronous clock from pin)
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time
2
Clock High time
2
Clock Low time
2
Input Rise time
2
Input Fall time
2
Maximum FF toggle rate
2
(1/T
CH
+ T
CL
)
Maximum internal frequency
2
(1/T
SUPAL
+ T
CF
)
Maximum external frequency
2
(1/T
SUPAL
+ T
CO
)
Output buffer delay time
2
Input (or feedback node) to internal feedback node delay time through
PAL
2
Input (or feedback node) to internal feedback node delay time through
PAL + PLA
2
Clock to internal feedback node delay time
2
Delay from valid V
CC
to valid reset
2
Input to output disable
2, 3
Input to output valid
2
Input to register preset
2
Input to register reset
2
ns
ns
T
CO
T
SU_PAL
T
SU_PLA
T
H
T
CH
T
CL
T
R
T
F
f
MAX1
f
MAX2
f
MAX3
T
BUF
T
PDF_PAL
2
5
7
-
-
0
-
-
2
6
8
-
-
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
6.5
7.5
3
3
-
-
3.5
3.5
-
-
143
95
77
-
-
100
100
-
-
-
2
8
100
100
-
-
-
2
9
166
111
90
-
-
T
PDF_PLA
-
9.5
-
10.5
ns
T
CF
T
INIT
T
ER
T
EA
T
RP
T
RR
Notes:
-
-
-
-
-
-
5
-
-
-
-
-
-
5.5
20
12
12
12
12
ns
μ
s
ns
ns
ns
ns
20
10
10
10
10
1. Specifications measured with one output switching. See
Figure 6
and
Table 6
for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C
L
= 5 pF.
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