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參數(shù)資料
| 型號(hào)： | XCR22V10-7VO24C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | 5V Zero Power, TotalCMOS, Universal PLD Device |
| 中文描述： | EE PLD, 7.5 ns, PDSO24 |
| 封裝： | THIN, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 145K |
| 代理商： | XCR22V10-7VO24C |
R
XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
5
www.xilinx.com
1-800-255-7778
DS048 (v1.1) February 10, 2000
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type
flip-flop (registered function). The D-type flip-flop latches
data on the rising edge of the clock and is controlled by the
global preset and clear terms. When the synchronous pre-
set term is satisfied, the Q output of the register will be set
High at the next rising edge of the clock input. Satisfying the
asynchronous clear term will set Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Program/Erase Cycles
The XCR22V10 is 100% testable, erases/programs in sec-
onds, and guarantees 1000 program/erase erase cycles.
Output Polarity
Each macrocell can be configured to implement active High
or active Low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bidi-
rectional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically FALSE and
the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a regis-
tered function (S1=0) (
Figure 4
a or
Figure 4
b), the feed-
back signal to the AND array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combi-
natorial function (S1=1) (
Figure 4
c or
Figure 4
d), the feed-
back signal is taken from the I/O pin. In this case, the pin
can be used as a dedicated input, a dedicated output, or a
bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a
reset condition and the Q output will be low. The actual out-
put of the XCR22V10 will depend on the programmed out-
put polarity. The V
CC
rise must be monotonic.
Design Security
The XCR22V10 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set, it is impossible to
verify (read) or program the XCR22V10 until the entire
device has first been erased with the bulk-erase function.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS SPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer SPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must accept low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of our XCR22V10 TotalCMOS SPLD.
Table 1: Typical I
CC
vs. Frequency @ V
CC
= 5V, 25
°
C
Frequency (MHz)
1
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
Tupical I
CC
(mA)
0.5
1.9
3.5
5.0
6.5
8.1
9.5
10.9
12.4
13.9
15.4
16.7
18.1
19.4
20.7
22.1
23.5
24.8
26.2
27.5
28.7
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