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參數(shù)資料
| 型號： | XCF32PVOG48 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng) |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 525K |
| 代理商： | XCF32PVOG48 |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
19
R
Figure 11:
Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be tied to
VCCO via a 4.7 k
Ω
pull-up resistor.
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK
CE
CEO
OE/RESET
CF
(5)
BUSY
(4)
TDO
Xilinx FPGA
Master SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
TDI
TMS
TCK
GND
MODE PINS
(1)
TDO
V
CCJ
V
CCO
V
CCINT
4
Ω
4
Ω
(1)
V
CCO(2)
TDI
TMS
TCK
TDO
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
TDI
TMS
TCK
GND
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK
CE
CEO
OE/RESET
CF
(5)
BUSY
(4)
TDO
V
CCJ
V
CCO
V
CCINT
MODE PINS
(1)
TDO
ds123_16_122105
1
Ω
1
Ω
I/O
(3)
I/O
(3)
1
Ω
1
Ω
I/O
(3)
I/O
(3)
RDWR_B
CS_B
RDWR_B
CS_B
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