參數(shù)資料
型號(hào)： XCF32PVO48C
廠商： XILINX INC
元件分類： DRAM
英文描述： Platform Flash In-System Programmable Configuration PROMS
中文描述： 32M X 1 CONFIGURATION MEMORY, PDSO48
封裝： PLASTIC, TSOP-48
文件頁(yè)數(shù)： 15/46頁(yè)
文件大小： 525K
代理商： XCF32PVO48C
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
15
R
Figure 7:
Configuring in Slave Serial Mode
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive the
FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then CLKOUT must
be tied to a 4.7K
Ω
resistor pulled up to V
CCO
.
4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
For the
XCFxxP, if CF is not connected to PROGB, then it must be tied to V
CCO
via a 4.7 k
Ω
pull-up resistor.
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
MODE PINS
(1)
DOUT
TDO
V
CCJ
V
CCO
V
CCINT
DIN
CCLK
DONE
INIT_B
PROG_B
DIN
CCLK
DONE
INIT_B
PROG_B
4
Ω
4
Ω
(1)
V
CCO(2)
...OPTIONAL
Daisy-chained
Slave FPGAs
with
different
configurations
...OPTIONAL
Slave FPGAs
with
identical
configurations
TDI
TMS
TCK
TDO
Platform Flash
PROM
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
GND
D0
CLK
(3)
CE
CEO
OE/RESET
CF
(4)
TDO
ds123_12_122105
External
(3)
Oscillator
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