參數(shù)資料
型號(hào)： XCF32PVG
廠商： Xilinx, Inc.
英文描述： Platform Flash In-System Programmable Configuration PROMS
中文描述： 平臺(tái)Flash在系統(tǒng)可編程配置方案管理系統(tǒng)
文件頁數(shù)： 44/46頁
文件大?。?/td> 525K
代理商： XCF32PVG
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
44
R
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
04/29/03
1.0
Xilinx Initial Release.
06/03/03
1.1
Made edits to all pages.
11/05/03
2.0
Major revision.
11/18/03
2.1
Pinout corrections as follows:
Table 14
:
For VO48 package, removed 38 from VCCINT and added it to VCCO.
For FS48 package, removed pin D6 from VCCINT and added it to VCCO.
Table 15
(FS48 package):
For pin D6, changed name from VCCINT to VCCO.
For pin A4, changed name from GND to DNC.
Figure 16
(VO48 package): For pin 38, changed name from VCCINT to VCCO.
12/15/03
2.2
Added specification (4.7k
Ω)
for recommended pull-up resistor on OE/RESET pin to section
"Reset and Power-On Reset Activation," page 22
.
Added paragraph to section
"Standby Mode," page 22
, concerning use of a pull-up resistor
and/or buffer on the DONE pin.
05/07/04
2.3
Section
"Features," page 1
: Added package styles and 33 MHz configuration speed limit to
itemized features.
Section
"Description," page 1
and following: Added state conditions for CF and BUSY to the
descriptive text.
Table 2, page 3
: Updated Virtex-II configuration bitstream sizes.
Section
"Design Revisioning," page 9
: Rewritten.
Section
"PROM to FPGA Configuration Mode and Connections Summary," page 10
and
following, five instances: Added instruction to tie CF High if it is not tied to the FPGA’s PROG_B
(PROGRAM) input.
Figure 6, page 14
, through
Figure 13, page 21
: Added footnote indicating the directionality of the
CF pin in each configuration.
Section
"I/O Input Voltage Tolerance and Power Sequencing," page 22
: Rewritten.
Table 12, page 23
: Added CF column to truth table, and added an additional row to document
the Low state of CF.
Section
"Absolute Maximum Ratings," page 24
: Revised V
IN
and V
TS
for ’P’ devices.
Section
"Supply Voltage Requirements for Power-On Reset and Power-Down," page 24
:
Revised footnote callout number on T
OER
from Footnote (4) to Footnote (3).
Added Footnote (2) callout to T
VCC
.
Section
"Recommended Operating Conditions," page 25
:
Added Typical (Typ) parameter columns and parameters for V
CCINT
and V
CCO
/V
CCJ
.
Added 1.5V operation parameter row to V
IL
and V
IH
, ’P’ devices.
Revised V
IH
Min, 2.5V operation, from 2.0V to 1.7V.
Added parameter row T
IN
and Max parameters
(Continued on next page)
05/07/04
(cont’d)
2.3
(cont’d)
Section
"DC Characteristics Over Operating Conditions," page 26
:
Added parameter row and parameters for parallel configuration mode, ’P’ devices, to I
CCO
.
Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column for I
CCJ
,
I
CCINTS
, I
CCOS
, and I
CCJS
, to define active and standby mode requirements.
Section
"AC Characteristics Over Operating Conditions," page 27
:
Corrected description for second T
CAC
parameter line to show parameters for 1.8V V
CCO
.
Revised Footnote (7) to indicate V
CCO
= 3.3V.
Applied Footnote (7) to second T
CYC
parameter line.
Section
"AC Characteristics Over Operating Conditions When Cascading," page 36
: Revised
Footnote (5)T
CYC
Min and T
CAC
Min formulas.
Table 14, page 39
:
Added additional state conditions to CLK description.
Added function of resetting the internal address counter to CF description.
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