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參數(shù)資料
| 型號： | XCF16PVO48 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng) |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 525K |
| 代理商： | XCF16PVO48 |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
5
R
Reliability and Endurance
Xilinx in-system programmable products provide a
guaranteed endurance level of 20,000 in-system
program/erase cycles and a minimum data retention of 20
years. Each device meets all functional, performance, and
data retention specifications within this endurance limit.
Design Security
The Xilinx in-system programmable Platform Flash PROM
devices incorporate advanced data security features to fully
protect the FPGA programming data against unauthorized
reading via JTAG. The XCFxxP PROMs can also be
programmed to prevent inadvertent writing via JTAG.
Table 4
and
Table 5
show the security settings available for
the XCFxxS PROM and XCFxxP PROM, respectively.
Read Protection
The read protect security bit can be set by the user to
prevent the internal programming pattern from being read or
copied via JTAG. Read protection does not prevent write
operations. For the XCFxxS PROM, the read protect
security bit is set for the entire device, and resetting the read
protect security bit requires erasing the entire device. For
the XCFxxP PROM the read protect security bit can be set
for individual design revisions, and resetting the read
protect bit requires erasing the particular design revision.
Write Protection
The XCFxxP PROM device also allows the user to write
protect (or lock) a particular design revision to prevent
inadvertent erase or program operations. Once set, the
write protect security bit for an individual design revision
must be reset (using the UNLOCK command followed by
ISC_ERASE command) before an erase or program
operation can be performed.
IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is compatible with the IEEE
1149.1 boundary-scan standard and the IEEE 1532
in-system configuration standard. A Test Access Port (TAP)
and registers are provided to support all required boundary
scan instructions, as well as many of the optional
instructions specified by IEEE Std. 1149.1. In addition, the
JTAG interface is used to implement in-system programming
(ISP) to facilitate configuration, erasure, and verification
operations on the Platform Flash PROM device.
Table 6,
page 6
lists the required and optional boundary-scan
instructions supported in the Platform Flash PROMs. Refer
to the IEEE Std. 1149.1 specification for a complete
description of boundary-scan architecture and the required
and optional instructions.
Caution!
The XCFxxP JTAG TAP pause states are not fully compliant with
the JTAG 1149.1 specification. If a temporary pause of a JTAG shift operation is
required, then stop the JTAG TCK clock and maintain the JTAG TAP within the
JTAG Shift-IR or Shift-DR TAP state. Do not transition the XCFxxP JTAG TAP
through the JTAG Pause-IR or Pause-DR TAP state to temporarily pause a
JTAG shift operation.
Instruction Register
The Instruction Register (IR) for the Platform Flash PROM
is connected between TDI and TDO during an instruction
scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI.
XCFxxS Instruction Register (8 bits wide)
The Instruction Register (IR) for the XCFxxS PROM is eight
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in
Table 7, page 6
.
The instruction capture pattern shifted out of the XCFxxS
device includes IR[7:0]. IR[7:5] are reserved bits and are set
to a logic 0. The ISC Status field, IR[4], contains logic 1 if
the device is currently in In-System Configuration (ISC)
mode; otherwise, it contains logic 0. The Security field,
IR[3], contains logic 1 if the device has been programmed
with the security option turned on; otherwise, it contains
Table 4:
XCFxxS Device Data Security Options
Read Protect
Read/Verify
Inhibited
Program
Inhibited
Erase
Inhibited
Reset (default)
Set
Table 5:
XCFxxP Design Revision Data Security Options
Read Protect
Write Protect
Read/Verify
Inhibited
Program Inhibited
Erase Inhibited
Reset (default)
Reset (default)
Reset (default)
Set
Set
Reset (default)
Set
Set
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相關代理商/技術參數(shù) |
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| XCF16PVO48C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述:Serial EEPROM, 48 Pin, Plastic, TSSOP |
| XCF16PVO48C | 制造商:Xilinx 功能描述: |
| XCF16PVO48C0973 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XCF16PVO48CESB | 制造商:Xilinx 功能描述: |
| XCF16PVOG48 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS |
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