參數(shù)資料
型號: XCF16PVO48
廠商: Xilinx, Inc.
英文描述: Platform Flash In-System Programmable Configuration PROMS
中文描述: 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng)
文件頁數(shù): 20/46頁
文件大?。?/td> 525K
代理商: XCF16PVO48
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
20
R
Figure 12:
Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
D0
CLK
(3)
CE
CEO
OE/RESET
CF
(4)
TDO
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
V
CCJ
V
CCO
V
CCINT
4
Ω
4
Ω
(1)
V
CCO(2)
TDI
TMS
TCK
TDO
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
D0
CLK
(3)
CE
CEO
OE/RESET
CF
(4)
TDO
V
CCJ
V
CCO
V
CCINT
ds123_17_122105
Design
Revision
Control
Logic
EN_EXT_SEL
REV_SEL[1:0]
DONE
CF / PROG_B
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
MODE PINS
(1)
TDO
GND
GND
GND
DOUT
MODE PINS
(1)
GND
External
(3)
Oscillator
Notes
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT
signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used,
then CLKOUT must be tied to a 4.7 K
Ω
resistor pulled up to V
CCO
.
4. For the XCFxxP the CF pin is a bidirectional pin.
For the XCFxxP, if CF is not connected to PROGB, then it
must be tied to V
CCO
via a 4.7 k
Ω
pull-up resistor.
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