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參數(shù)資料
| 型號： | XC9536XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | FastFLASH High-Performance CPLD(FastFLASH 高性能復(fù)雜可編程邏輯器件) |
| 中文描述： | FastFLASH高性能的CPLD（FastFLASH高性能復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 143K |
| 代理商： | XC9536XL |
R
June 7, 1999 (Version 1.5)
5-19
FastFLASH XC9500XL High-Performance CPLD Family
5
Power-Up Characteristics
The XC9500XL devices are well behaved under all operat-
ing conditions. During power-up each XC9500XL device
employs internal circuitry which keeps the device in the qui-
escent state until the V
CCINT
supply voltage is at a safe
level (approximately 2.5 V). During this time, all device pins
and JTAG pins are disabled and all device outputs are dis-
abled with the pins weakly pulled high, as shown in
Table 5
.
When the supply voltage reaches a safe level, all user reg-
isters become initialized (typically within 200
μ
s), and the
device is immediately available for operation, as shown in
Figure 17
.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
weak pull-up. The JTAG pins are enabled to allow the
device to be programmed at any time. All devices are
shipped in the erased state from the factory.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
Development System Support
The XC9500XL family and associated in-system program-
ming capabilities are fully supported in either software solu-
tions available from Xilinx.
The Foundation Series is an all-in-one development sys-
tem containing schematic entry, HDL (VHDL, Verilog, and
ABEL), and simulation capabilities. It supports the
XC9500XL family as well as other CPLD and FPGA fami-
lies.
The Alliance Series includes CPLD and FPGA implementa-
tion technology as well as all necessary libraries and inter-
faces for Alliance partner EDA solutions.
FastFLASH Technology
An advanced 0.35 micron feature size CMOS Flash process is
used to fabricate all XC9500XL devices. The FastFLASH pro-
cess provides high performance logic capability, fast pro-
gramming times, and superior reliability and endurance
ratings.
Table 4: Timing Model Parameters
Note:
1. S = the logic span of the function, as defined in the text.
Table 5: XC9500XL Device Characteristics
V
CCINT
No
Power
3.8 V
(Typ)
0 V
No
Power
Quiescent
State
Quiescent
State
User Operation
Initialization of User Registers
X5904
Figure 17: Device Behavior During Power-up
Description
Parameter
Product Term
Allocator
1
+ t
PTA
*
S
+ t
PTA
*
S
–
+ t
PTA
*
S
Macrocell
Low-Power Setting
+ t
LP
+ t
LP
–
+ t
LP
Output Slew-Limited
Setting
+ t
SLEW
–
+ t
SLEW
–
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup
Time
Product Term Clock-to-output
Internal System Cycle Period
t
PD
t
SU
t
CO
t
PSU
t
PCO
t
SYSTEM
–
–
+ t
SLEW
–
+ t
PTA
*
S
+ t
LP
Device
Circuitry
Quiescent
State
Pull-up
Disabled
Disabled
Disabled
Disabled
Erased Device
Operation
Pull-up
Disabled
Disabled
Disabled
Enabled
Valid User
Operation
Bus-Hold
As Configured
As Configured
As Configured
Enabled
IOB Bus-Hold
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller
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