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參數(shù)資料
| 型號： | XC95108 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復雜可編程邏輯器件） |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 74K |
| 代理商： | XC95108 |
Designing with XC9500 CPLDs
2-26
XAPP073 January, 1998 (Version 1.3)
All digital ICs have this property. No harm is caused to the
system unless the voltage swing on the static output is
capable of switching another circuit down the line. Prob-
lems can occur if the voltage swing is excessive. This effect
is particularly significant if the static (quiet) signal is
attached to another circuit’s clock input.
Two factors contribute to this ground rise. First, the amount
of capacitive load being driven is important because charge
on this capacitance is the source of the in rushing current.
Second, the number of simultaneous switching outputs is a
factor since each switching output adds to the total capaci-
tance being discharged.
XC9500 devices are in symmetric packages with multiple
ground pins. However, some designs may need more
grounding, and therefore the XC9500 family includes user
programmable ground pins that allow the device I/O pins to
be configured as additional grounds. Tying programmable
ground pins to the external ground connection reduces sys-
tem noise. The Xilinx XACTstepsoftware can be used to
connect unused macrocell outputs to ground.
The following checklist will help reduce unnecessary
ground noise:
1. Only connect the essential outputs to I/O pins. Interme-
diate shift register bits and counter bits that need not
drive outputs should remain buried.
2. Minimize the number of outputs switching simulta-
neously.
3. Two global clock or GTS inputs can be managed by
delaying one of the signals to gain signal skew.
4. Using additional ground pins can lower ground rise
effects. Unused pins configured as grounds can be tied
directly to the PC board ground plane. This splits the
current driven into heavily loaded ground pins and low-
ers the voltage rise.
5. Signal skewing can also reduce ground rise. This can be
achieved by mixing ordinary and fast slew rate outputs.
Only assign the fast slew rate to signals that require it.
Conclusion
By using the techniques described in this application note,
designers can achieve the highest-performance logic using
the XC9500 family. The XC9500 family datasheet contains
additional descriptions of the important system features.
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| XC95216-15BG352I | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:12; Connector Shell Size:28; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC95108-10PC84C | 功能描述:IC CPLD 108 MCELL C-TEMP 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95108-10PC84I | 功能描述:IC CPLD 108 MCELL I-TEMP 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95108-10PCG84C | 制造商:Xilinx 功能描述:XLXXC95108-10PCG84C IC SYSTEM GATE |
| XC95108-10PQ100C | 功能描述:IC CPLD 108 MACROCELL 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95108-10PQ100C0586 | 制造商:Xilinx 功能描述: |
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