參數(shù)資料
型號(hào)： XC6VCX195T-2FFG784I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 37/52頁(yè)
文件大小： 0K
描述： IC FPGA VIRTEX 6 199K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 15600
邏輯元件/單元數(shù)： 199680
RAM 位總計(jì)： 12681216
輸入/輸出數(shù)： 400
電源電壓： 0.95 V ~ 1.05 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
42
Configuration Switching Characteristics
Table 52: Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Power-up Timing Characteristics
TPL(1)
Program Latency
3
ms, Max
TPOR(1)
Power-on-Reset
15/55
ms, Min/Max
TICCK
CCLK (output) delay
400
ns, Min
TPROGRAM
Program Pulse Width
250
ns, Min
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD
DIN Setup/Hold, slave mode
4.0/0.0
ns, Min
TDSCCK/TSCCKD
DIN Setup/Hold, master mode
4.0/0.0
ns, Min
TCCO
DOUT at 2.5V
6
ns, Max
DOUT at 1.8V
6
ns, Max
FMCCK
Maximum CCLK frequency, serial modes
100
MHz, Max
FMCCKTOL
Frequency Tolerance, master mode with respect to
nominal CCLK
55
%
FMSCCK
Slave mode external CCLK
100
MHz
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
4.0/0.0
ns, Min
TSMCSCCK/TSMCCKCS
CSI_B Setup/Hold
4.0/0.0
ns, Min
TSMCCKW/TSMWCCK
RDWR_B Setup/Hold
10.0/0.0
ns, Min
TSMCKCSO
CSO_B clock to out
(330
pull-up resistor required)
77
ns, Min
TSMCO
CCLK to DATA out in readback at 2.5V
8
ns, Max
CCLK to DATA out in readback at 1.8V
8
ns, Max
TSMCKBY
CCLK to BUSY out in readback at 2.5V
6
ns, Max
CCLK to BUSY out in readback at 1.8V
6
ns, Max
FSMCCK
Maximum Frequency with respect to nominal CCLK
100
MHz, Max
FRBCCK
Maximum Readback Frequency with respect to nominal
CCLK
100
MHz, Max
FMCCKTOL
Frequency Tolerance with respect to nominal CCLK
55
%
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP
TMS and TDI Setup time before TCK/ Hold time after
TCK
3.0/2.0
ns, Min
TTCKTDO
TCK falling edge to TDO output valid at 2.5V
6
ns, Max
TCK falling edge to TDO output valid at 1.8V
6
ns, Max
FTCK
Maximum configuration TCK clock frequency
66
MHz, Max
FTCKB_MIN
Minimum boundary-scan TCK clock frequency when
using IEEE Std 1149.6 (AC-JTAG). Minimum operating
temperature for IEEE Std 1149.6 is 0°C.
15
MHz, Min
FTCKB
Maximum boundary-scan TCK clock frequency
66
MHz, Max
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