參數(shù)資料
型號： XC6SLX100T-2FG676I
廠商： Xilinx Inc
文件頁數(shù)： 86/89頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 676FGGBGA
標準包裝： 40
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 7911
邏輯元件/單元數(shù)： 101261
RAM 位總計： 4939776
輸入/輸出數(shù)： 376
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應商設備封裝： 676-FBGA（27x27）
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
87
01/10/11
1.11
Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in Table 26 and
Table 27 using ISE v12.4 software with speed specification v1.15 for the -4, -3, -3N, and -2 speed
grades. Added note 3 to Table 27. Also updated the -1L speed grade requirements to ISE v12.4
software with speed specification v1.06. Revised -3N definition throughout the document.
Added note 4 to Table 2 and updated note 5. Added information on VCCINT to note 1 in Table 5.
Updated Networking Applications -3 values in Table 25 to match improvements made in ISE v12.4. In
Table 28, added note 1 and revised the TIOTP values for LVDS_33, LVDS_25, MINI_LVDS_33,
MINI_LVDS_25, RSDS_33, RSDS_25, TMDS_33. PPDS_33, and PPDS_25. Added note 3 to
02/11/11
1.12
As described in XCN11008: Product Discontinuation Notice For Spartan-6 LXT -4 Devices, the -4
speed specifications have been discontinued. As outlined in page 2 of the XCN, designers currently
using -4 speed specifications should rerun timing analysis using the new -3 speed specifications before
moving to a replacement device.
Updated the networking applications section of Table 25. Updated -2 speed specifications throughout
document and added note 3 to Table 27 advising designers to use the -2 speed specification update
(v1.17) with the ISE 12.4 software patch. Added FCLKDIV to Table 37 and Table 38. Updated note 2 in
Table 39. Updated units for TSMCKCSO and TBPICCO in Table 47. Updated -1L in Table 71. Removed
Note 2: Package delay information is available for these device/package combinations. This
information can be used to deskew the package from Table 79.
03/31/11
2.0
Production release of XC6SLX45 in the -1L speed grades listed in Table 26 and Table 27 using ISE
v13.1 software with -1L speed specification v1.06.
In Table 39, removed values in the -1L column and added note 3 as IODELAY2 only supports Tap0 for
lower-power devices. Updated copyright page 1 and Notice of Disclaimer.
05/20/11
2.1
Production release of XC6SLX100 and XC6SLX150 in the specific speed grades listed in Table 26 and
Table 27 using ISE v13.1 software with -1L speed specification v1.06. Updated Table 27 and Note 7
with changes per XCN11012: Speed File Change for -3N Devices. Revised Switching Characteristics
section for speed specifications: v1.18 for -3, -3N, and -2; including improvements in Table 73 through
Removed Memory Controller Block from the performance heading in Table 2 and revised Note 2. In
Table 4, added Note 1 to CIN and updated the description of RIN_TERM. Updated Note 1 in Table 5.
Updated Note 1 of Table 7. In Table 25, added and removed -1L specifications, increased the standard
performance DDR3 specifications, removed the extended performance DDR3 row and updated Note 3
and Note 4. Clarified the introductory information for Table 28 and Table 30.
In Table 32: Revised VMEAS value for LVCMOS12; revised VREF for LVDS_25, LVDS_33,
BLVDS_25,MINI_LVDS_25, MINI_LVDS_33, RSDS_25, and RSDS_33; revised RREF for BLVDS_25
and TMDS_33; and added Note 4 and Note 5. Updated Note 2 and Note 3 in Table 39.
In Table 47, revised the values and description of TPOR including adding Note 3. Also in Table 47,
augmented the description and added specifications for FRBCCK and removed XC6SLX4 from FMCCK
(maximum frequency, parallel mode (Master SelectMAP/BPI). Added BUFGMUX to Table 48 title.
Added Table 50.
In Table 52, revised specifications for TEXTFDVAR and FINJITTER. In Table 54 removed the 5 MHz <
CLKIN_FREQ_DLL parameter in the LOCK_DLL description. In both Table 56 and Table 57, removed
the 5 MHz < FCLKIN parameter in the LOCK_FX description. In Table 58, updated description for
PSCLK_FREQ and PSCLK_PULSE.
Revised title and symbol of Table 70, added new speed specifications for -1L, and added Note 2.
Added Table 71.
07/11/11
2.2
Added the Automotive XA Spartan-6 and Defense-grade Spartan-6Q devices to all appropriate tables
while sometimes removing the XC6S nomenclature. Added expanded temperature range (Q) to all
appropriate tables. Updated TSOL packages in Table 1. Added ROUT_TERM to Table 4. Updated Note 2
Production release of the XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX75, XQ6SLX75, and
XQ6SLX150 in Table 26 and Table 27 using ISE v13.2 software with -1L speed specification v1.07.
Production release of the XA6SLX16, XA6SLX25T, XA6SLX45, XA6SLX45T, XQ6SLX75,
XQ6SLX75T, XQ6SLX150, and XQ6SLX150T in Table 26 and Table 27 using ISE v13.2 software with
-2 and -3 speed specification v1.19.
Devices(1). Updated CS(G)484 from CSG484 throughout data sheet. Clarified Note 3 in Table 39.
08/08/11
2.3
Production release of the XA6SLX25, XA6SLX75, and XA6SLX75T in Table 26 and Table 27 using ISE
v13.2 software with -2 and -3 speed specification v1.19.
Date
Version
Description of Revisions
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相關代理商/技術參數(shù)
參數(shù)描述
XC6SLX100T-2FG900C 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 101261 CELLS 45NM (CMOS) TECHNOLOGY 1 - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 101K 900BGA
XC6SLX100T-2FG900I 功能描述:IC FPGA SPARTAN 6 900FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6SLX100T-2FGG484C 功能描述:IC FPGA SPARTAN 6 101K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6SLX100T-2FGG484I 功能描述:IC FPGA SPARTAN 6 101K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6SLX100T-2FGG676C 功能描述:IC FPGA SPARTAN 6 101K 676FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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